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-A universal asynchronous receiver/transmitter,​ abbreviated ​UART /​ˈjuːɑːrt/, ​is a computer hardware device that translates data between characters (usually bytes) in a computer and an asynchronous serial communication format that encapsulates those characters between start bits and stop bits. UARTs are commonly used in conjunction with communication standards such as TIA (formerly ​EIA) RS-232, RS-422 ​or RS-485. The universal designation indicates that the data format and transmission speeds are configurable. The electric signaling levels and methods (such as differential signaling etc.) are handled by a driver circuit external to the UART.+## UART - 异步串行通信 
 +一个通用的异步接收/发射器，简称为UART /​ˈjuːɑːrt/, ​是一种计算机硬件设备，它在计算机中的字符（通常是字节）之间转换数据，以及在起始位和停止位之间封装这些字符的异步串行通信格式,​ 其中数据格式和传输速度是可配置的。UART通常与通信标准结合使用，例如TIA（以前称为EIA）[[RS-232]]，RS-422或RS-485。 通用名称表示数据格式和传输速度是可配置的。 电信号电平和方法（例如差分信号等）由UART外部的驱动电路处理。
  
-A UART is usually an individual (or part of an) integrated circuit (IC) used for serial communications over a computer or peripheral device serial port. UARTs are now commonly included in microcontrollers. A dual UART, or DUART, combines two UARTs into a single chip. An octal UART or OCTART ​combines eight UARTs into one package, such as the Exar XR16L788 ​or the NXP SCC2698. A related device, the Universal Synchronous/Asynchronous Receiver/Transmitter (USART) also supports synchronous operation.+UART通常是用于通过计算机或外围设备串行端口进行串行通信的单独（或部分）集成电路（IC）。 ​UART现在通常包含在微控制器中。 双UART或DUART将两个UART组合成一个芯片。 八进制UART或OCTART将八个UART组合成一个封装，例如Exar XR16L788或NXP SCC2698。 相关设备，通用同步/异步接收器/发送器（USART）也支持同步操作。
  
-====== Transmitting and receiving serial data ======+UART采用字节数据并以顺序方式发送各个位。在目的地，第二个UART将这些位重新组合成完整的字节。每个UART都包含一个移位寄存器，它是串行和并行形式之间转换的基本方法。通过单线或其他介质的数字信息（比特）的串行传输比通过多条线的并行传输更便宜。
  
-The universal asynchronous receiver/​transmitter (UART) takes bytes of data and transmits the individual bits in a sequential fashion.[ At the destination,​ a second ​UART re-assembles the bits into complete bytes. Each UART contains a shift register, which is the fundamental method of conversion between serial and parallel forms. Serial transmission of digital information (bits) through a single wire or other medium is less costly than parallel transmission through multiple wires.+UART通常不直接生成或接收不同设备之间使用的外部信号。独立的接口设备用于将UART的逻辑电平信号转换为外部信号电平和从外部信号电平转换。外部信号可以有许多不同的形式。电压信号标准的示例是来自EIA的[[RS-232]]，RS-422和RS-485。历史上，电流电路中使用电流（电流环路）。一些信令方案不使用电线。其示例是其串行端口配置文件（SPP）中的光纤，IrDA（红外线）和（无线）蓝牙。一些信令方案使用载波信号的调制（有或没有线路）。例如，使用电话线调制解调器调制音频信号，使用数据无线电调制RF调制，以及使用DC-LIN进行电力线通信。
  
-The UART usually does not directly generate or receive the external signals used between different items of equipment. Separate interface devices are used to convert the logic level signals of the UART to and from the external signalling levels. External signals may be of many different forms. Examples of standards for voltage signaling are RS-232, RS-422 and RS-485 from the EIA. Historically,​ current (in current loops) was used in telegraph circuits. Some signaling schemes do not use electrical wires. Examples of such are optical fiber, IrDA (infrared), and (wireless) Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use modulation of a carrier signal (with or without wires). Examples are modulation of audio signals with phone line modems, RF modulation with data radios, and the DC-LIN for power line communication.+通信可以是单工的（仅在一个方向上，没有规定接收设备将信息发送回发送设备），全双工（两个设备同时发送和接收）或半双工（设备轮流发送和接收） ）。
  
-Communication may be simplex (in one direction only, with no provision for the receiving device to send information back to the transmitting device), full duplex (both devices send and receive at the same time) or half duplex (devices take turns transmitting and receiving). 
  
-===== Data framing =====+### 1. UART的工作原理
  
-Bit number 1 2 3 4 5 6 7 8 9 10 11 12 +UART（Universal Asynchronous Receiver/​Transmitter，翻译过来叫通用异步收发） 其实不是像SPI和I2C这样的通信协议，而是MCU（微控制器）中的物理电路或独立的IC，它的主要用途是发送和接收串行数据。
-Start bit 5–9 data bits Stop bit(s) +
-Start Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Stop +
-The idle, no data state is high-voltage,​ or powered. This is a historic legacy from telegraphy, in which the line is held high to show that the line and transmitter are not damaged. Each character is sent as a logic low start bit, a configurable number of data bits (usually 8, but users can choose 5 to 8 or 9 bits depending on which UART is in use), an optional parity bit if the number of bits per character chosen is not 9 bits, and one or more logic high stop bits. In most applications the least significant data bit (the one on the left in this diagram) is transmitted first, but there are exceptions (such as the IBM 2741 printing terminal).+
  
-The start bit signals the receiver that a new character is coming. The next five to nine bits, depending on the code set employed, represent the character. If a parity bit is used, it would be placed after all of the data bits. The next one or two bits are always in the mark (logic high, i.e., '​1'​) condition and called the stop bit(s). They signal the receiver that the character is completed. Since the start bit is logic low (0) and the stop bit is logic high (1) there are always at least two guaranteed signal changes between characters.+在UART通信中，两个UART可以直接相互通信。 发送UART将来自CPU等控制设备的并行数据转换为串行格式，并将其串行发送到接收端的UART，接收UART将串行数据转换回接收设备的并行数据。 在两个UART之间传输数据只需要两根线， 数据流从发送UART的Tx引脚到接收UART的Rx引脚：
  
-If the line is held in the logic low condition for longer than a character time, this is a break condition that can be detected by the UART.+{{ :uartp2s.png |}}<WRAP centeralign>​超简化的UART接口，左侧为并行，右侧为串行</​WRAP>​
  
-===== Receiver =====+通用异步接收器/​发送器（UART）是负责实现串行通信的电路块。 本质上，UART充当并行和串行接口之间的中介。 UART的一端是八条左右数据线（加上一些控制引脚），另一条是两条串行线 - RX和TX。
  
-All operations of the UART hardware are controlled by a clock signal which runs at a multiple of the data rate, typically 8 times the bit rate. The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, it is considered a spurious pulse and is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) have elapsed, the contents of the shift register are made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data.+{{ :uart_txrx.png |}}
  
-Communicating UARTs usually have no shared timing system apart from the communication signal. Typically, UARTs resynchronize their internal clocks on each change of the data line that is not considered a spurious pulse. Obtaining timing information in this manner, they reliably receive when the transmitter is sending at a slightly different speed than it should. Simplistic UARTs do not do this, instead they resynchronize on the falling edge of the start bit only, and then read the center of each expected data bit, and this system works if the broadcast data rate is accurate enough to allow the stop bits to be sampled reliably.+两个设备可以发送和接收数据的串行接口是全双工或半双工。 全双工意味着两个设备可以同时发送和接收。 半双工通信意味着串行设备必须轮流发送和接收。
  
-It is a standard feature for a UART to store the most recent character while receiving the next. This "​double buffering"​ gives a receiving computer an entire character transmission time to fetch a received character. Many UARTs have a small first-in, first-out FIFO buffer memory between the receiver shift register and the host system interface. This allows the host processor even more time to handle an interrupt from the UART and prevents loss of received data at high rates.+UART以异步方式发送数据，也就是说没有时钟信号将发送UART的位输出与接收UART的位采样进行同步。 发送UART将“起始”和“停止”位添加到正在传输的数据包中， 这些位定义了数据包的开始和结束，接收UART基于这些位的信息知道何时开始读取输入的串行数据。
  
-===== Transmitter =====+当接收UART检测到起始位时，它以特定的频率（也就是“波特率”）读取输入的串行数据。波特率是数据传输速度的度量，单位-每秒位数（bps）。 两个UART必须以相同的波特率运行。发送和接收UART之间的波特率相差不能超过10%，偏差太远就无法对数据进行正确的解读。
  
-Transmission operation is simpler as the timing does not have to be determined from the line state, nor is it bound to any fixed timing intervals. As soon as the sending system deposits a character in the shift register (after completion of the previous character), the UART generates a start bit, shifts the required number of data bits out to the line, generates and sends the parity bit (if used), and sends the stop bits. Since full-duplex operation requires characters to be sent and received at the same time, UARTs use two different shift registers for transmitted and received characters. High performance UARTs could contain a transmit FIFO (first in first out) buffer to allow a CPU or DMA controller to deposit multiple characters in a burst into the FIFO rather than have to deposit one character at a time into the FIFO. Since transmission of a single or multiple characters may take a long time relative to CPU speeds, a UART maintains a flag showing busy status so that the host system knows if there is at least one character in the transmit buffer or shift register; "ready for next character(s)"​ may also be signaled with an interrupt.+当然两个UART还必须配置为发送和接收相同的数据包结构。
  
-===== Application =====+异步通信以一个字符为传输单位，通信中两个字符间的时间间隔多少是不固定的，然而在同一个字符中的两个相邻位间的时间间隔是固定的。两个相邻位间的时间间隔与UART通信的波特率有关，波特率用来表征UART通信中数据传输的速率，即每秒钟传送的二进制位数。例如数据传送速率为120字符/​秒，而每一个字符为10位（1个起始位，7个数据位，1个校验位，1个结束位），则其传送的波特率为10×120＝1200字符/​秒＝1200波特。
  
-Transmitting and receiving UARTs must be set for the same bit speed, character length, parity, and stop bits for proper operation. The receiving UART may detect some mismatched settings and set a "​framing error" flag bit for the host system; in exceptional cases the receiving UART will produce an erratic stream of mutilated characters and transfer them to the host system.+我们在调试种最比较常见的波特率是9600bps，其它的“标准”波特还有1200、2400、4800、19200、38400、57600和115200。
  
-Typical serial ports used with personal computers connected to modems use eight data bits, no parity, and one stop bit; for this configuration the number of ASCII characters per second equals the bit rate divided by 10.+以9600bps传输为例，将每个位高或低保持的时间为1 /（9600 bps）或每位104μs，对于发送的每个数据字节，实际上发送了10位：起始位，8个数据位和一个停止位。 因此，在9600bps时，我们实际上每秒发送9600位或每秒960（9600/​10）字节。
  
-Some very low-cost home computers or embedded systems dispense with a UART and use the CPU to sample the state of an input port or directly manipulate an output port for data transmission. While very CPU-intensive (since the CPU timing is critical), the UART chip can thus be omitted, saving money and space. The technique is known as bit-banging.+波特率越高，发送/​接收的数据越快，但数据传输的速度有限。您通常不会看到超过115200的速度 ​- 这对于大多数微控制器来说都很快。太高了，你会开始看到接收端的错误，因为时钟和采样周期无法跟上。
  
-====== History ====== 
  
 +{{ :​uart_baud.jpg |}}
  
-Some early telegraph schemes used variable-length pulses (as in Morse code) and rotating clockwork mechanisms to transmit alphabetic characters. The first serial communication devices (with fixed-length pulses) were rotating mechanical switches (commutators). Various character codes using 5, 6, 7, or 8 data bits became common in teleprinters and later as computer peripherals. The teletypewriter made an excellent general-purpose I/O device for a small computer.+#### 数据帧构成 
 +发送的每个数据块（通常是一个字节）实际上是以比特或比特帧发送的。通过将同步和奇偶校验位附加到数据来创建帧。 
 +{{ :uart_frame.jpg |}}
  
-Gordon Bell of DEC designed the first UART, occupying an entire circuit board called a line unit, for the PDP series of computers beginning with the PDP-1.[2][3] According to Bell, the main innovation of the UART was its use of sampling to convert the signal into the digital domain, allowing more reliable timing than previous circuits that used analog timing devices with manually adjusted potentiometers.[4] To reduce the cost of wiring, backplane and other components, these computers also pioneered flow control using XON and XOFF characters rather than hardware wires.+  * 起始位：先发出一个逻辑”0”信号，表示传输字符的开始。 
 +  * 数据位：可以是5~8位逻辑”0”或”1”。如ASCII码（7位），扩展BCD码（8位）。小端传输 
 +  * 校验位：数据位加上这一位后，使得“1”的位数应为偶数(偶校验)或奇数(奇校验) 
 +  * 停止位：它是一个字符数据的结束标志。可以是1位、1.5位、2位的高电平。 
 +  * 空闲位：处于逻辑“1”状态，表示当前线路上没有资料传送。
  
-DEC condensed the line unit design into an early single-chip UART for their own use.[2] Western Digital developed this into the first widely available single-chip UART, the WD1402A, around 1971. This was an early example of a medium scale integrated circuit. Another popular chip was the SCN2651 from the Signetics 2650 family. 
  
-An example of an early 1980s UART was the National Semiconductor 8250. In the 1990s, newer UARTs were developed with on-chip buffers. This allowed higher transmission speed without data loss and without requiring such frequent attention from the computer. For example, the popular National Semiconductor 16550 has a 16 byte FIFO, and spawned many variants, including the 16C550, 16C650, 16C750, and 16C850.+下面我们详细介绍一下每一部分。
  
-Depending on the manufacturer,​ different terms are used to identify devices that perform the UART functions. Intel called their 8251 device a "​Programmable Communication Interface"​. MOS Technology 6551 was known under the name "​Asynchronous Communications Interface Adapter"​ (ACIA). The term "​Serial Communications Interface"​ (SCI) was first used at Motorola around 1975 to refer to their start-stop asynchronous serial interface device, which others were calling a UART. Zilog manufactured a number of Serial Communication Controllers or SCCs.+##### 数据块 
 +每个串行数据包的真正有营养的是它携带的数据，我们且称之为“数据块”，它没有具体的大小限制。 每个数据包中的数据量可以设置为5到9位。 标准数据的大小一般是最基本的8位字节，但其它大小也有其用途，有时候7位数据能比8位更高效，比如只是用来传输7位ASCII字符。
  
-After the RS-232 COM port was removed from most IBM PC compatible computers in the 2000s, an external USB-to-UART serial adapter cable was used to compensate for the loss. A major supplier of these chips is FTDI.[5]+在统一了字符长度后，两个串行设备也必须就其数据的字节顺序达成一致。 数据是最高位（msb）还是最低位先发送？ 缺省设定为首先传输最低有效位（lsb）。
  
-====== Structure ======+##### 同步位
  
-A UART usually contains the following components:+同步位是每个数据块传输的两个或三个特殊位。 它们是起始位和停止位，顾名思义，这些位标记了数据包的开头和结尾。 始终只有一个起始位，但停止位的数量可配置为一个或两个（通常情况下保留为一个）。
  
-  * a clock generator, usually a multiple of the bit rate to allow sampling in the middle of a bit period. +起始位始终是由从1到0的空闲数据线来指示，而停止位则将通过将该信号线保持为1而转换回空闲状态。
-  * input and output shift registers +
-  * transmit/​receive control +
-  * read/write control logic +
-  * transmit/​receive buffers (optional) +
-  * system data bus buffer (optional) +
-  * First-in, first-out (FIFO) buffer memory (optional) +
-  * Signals needed by a third party DMA controller (optional) +
-  * Integrated bus mastering DMA controller (optional)+
  
-====== Special receiver conditions ======+  * 起始位：单字节UART发送的第一位。 它表示数据线正在离开其空闲状态。 空闲状态通常为逻辑高，因此起始位为逻辑低。起始位是开销位， 这意味着它有助于接收器和发射器之间的通信，但不会传输有意义的数据。 
 +  * 停止位: 单字节UART传输的最后一位。 其逻辑电平与信号的空闲状态相同，即逻辑高， 这是另一个开销。
  
-===== Overrun error =====+##### 奇偶校验位 
 +奇偶校验是一种非常简单的低级错误检查方式，它分为两种方式：奇数或偶数。 为了产生奇偶校验位，数据字节的所有5-9位相加，并且求和的奇偶性决定该位是否置位。 例如，假设奇偶校验设置为偶数并且正被添加到数字字节（如0b01011101，这串数中有奇数（5）个1，奇偶校验位将被设置为1。相反，如果奇偶校验模式设置为奇数 ，奇偶校验位则为0。 
 + 
  
-An "​overrun error" occurs when the receiver cannot process the character that just came in before the next one arrives. Various devices have different amounts of buffer space to hold received characters. The CPU or DMA controller must service the UART in order to remove characters from the input buffer. If the CPU or DMA controller does not service the UART quickly enough and the buffer becomes full, an Overrun Error will occur, and incoming characters will be lost.+##### 同步和采样 
 +下面我们来看看没有时钟信号的数据在接收端是如何被正确解读的。
  
-===== Underrun error =====+没有时钟对数据做判决，这些数据毫无意义。 下图显示了原因：
  
 +{{ :​uart_samping.jpg |}}
  
-An "​underrun error" occurs when the UART transmitter has completed sending a character and the transmit buffer is empty. In asynchronous modes this is treated as an indication that no data remains to be transmitted,​ rather than an error, since additional stop bits can be appended. This error indication is commonly found in USARTs, since an underrun is more serious in synchronous systems.+ ​同一串数据可以有不同的解读
  
-===== Framing error =====+典型的数据信号只是在逻辑低和逻辑高之间转换的电压。 只有当接收器知道何时采样信号时，接收器才能正确地将这些逻辑状态转换为数字数据。
  
 +这可以使用单独的时钟信号轻松完成 - 例如，发送器在时钟的每个上升沿更新数据信号，然后接收器在每个下降沿采样数据。但UART接口没有时钟信号来同步Tx和Rx器件，接收端如何知道何时采样发射端送来的数据信号呢？
  
-A "​framing error" occurs when the designated "​start"​ and "​stop"​ bits are not found. As the "​start"​ bit is used to identify the beginning of an incoming character, it acts as a reference for the remaining bits. If the data line is not in the expected state (hi/lo) when the "​stop"​ bit is expected, a Framing Error will occur.+发送端根据其时钟信号生成比特流，然后接收端的目标是使用其内部时钟信号在每个比特周期的中间对输入的数据流进行采样。虽然在比特周期的中间进行采样不是必要的但却是最佳的，因为接近比特周期的开始或结束的采样使得系统对接收端和发射端之间的时钟频率差异的鲁棒性较差。
  
-===== Parity error =====+接收端序列从起始位的下降沿开始，这是关键同步过程发生的时间。接收端的内部时钟完全独立于发送端的内部时钟 - 换句话说，第一个下降沿可以对应于接收端时钟周期中的任何点：
  
 +{{ :​uarttiming.jpg |}}
 + 
 +为了确保接收端时钟的有效边沿能够在比特周期的中间附近发生，发送到接收端模块的波特率时钟的频率要比实际波特率高得多（比8或16或甚至32倍）。
  
-A Parity Error occurs when the parity of the number of 1 bits disagrees with that specified by the parity bit. Use of a parity bit is optional, so this error will only occur if parity-checking has been enabled.+假设一个比特周期对应于16个接收端时钟周期。 在这种情况下，同步和采样可以按如下方式进行：
  
-===== Break condition =====+  - 接收过程由起始位的下降沿启动。 
 +  - 接收端等待8个时钟周期，以便建立一个接近比特周期中间的采样点。 
 +  - 然后，接收端等待16个时钟周期，使其进入第一个数据位周期的中间。 
 +  - 第一个数据位被采样并存储在接收寄存器中，然后模块在采样第二个数据位之前等待另外16个时钟周期。 
 +  - 重复此过程直到所有数据位都被采样和存储，然后停止位的上升沿使UART接口返回其空闲状态。 ​
  
-A "break condition"​ occurs when the receiver input is at the "​space"​ (logic low, i.e., '​0'​) level for longer than some duration of time, typically, for more than a character time. This is not necessarily an error, but appears to the receiver as a character of all zero bits with a framing error. The term "​break"​ derives from current loop signaling, which was the traditional signaling used for teletypewriters. The "​spacing"​ condition of a current loop line is indicated by no current flowing, and a very long period of no current flowing is often caused by a break or other fault in the line.+{{ :​uart_bitstream.jpg |}}
  
-Some equipment will deliberately transmit the "​space"​ level for longer than a character as an attention signal. When signaling rates are mismatched, no meaningful characters can be sent, but a long "​break"​ signal can be a useful way to get the attention of a mismatched receiver to do something (such as resetting itself). Unix-like systems can use the long "​break"​ level as a request to change the signaling rate, to support dial-in access at multiple signaling rates.+### UART的优点和缺点 
 +没有任何一种通信方式和协议是完美的，因此没中方式都有其优点，也有其缺点，我们来看看UART的主要优缺点。
  
-====== ​UART models ======+#### UART的优点： 
 +  * 只需要使用两根信号线就可以实现全双工的数据传输（不算电源线） 
 +  * 无需时钟信号 
 +  * 有一个奇偶校验位提供硬件级别的错误检查 
 +  * 数据包的结构可以通过两端之间的协调来改变，比较灵活 
 +  * 有丰富的文档且被广泛使用的通信方式 
 +  * 相对比较容易配置和运行
  
-Model Description +#### UART的缺点： 
-WD1402A The first single-chip UART on general sale. Introduced about 1971. Compatible chips included the Fairchild TR1402A and the General Instruments AY-5-1013.[6] +  * 与并行通信以及USART相比，数据传输的速度较慢 
-Exar XR21V1410  +  * 帧的大小被限定为最多9位 
-Intersil 6402  +  * 不支持多个从设备或多个主设备的功能 
-CDP 1854 (RCA, now Intersil)  +  * 收发两个器件UART的波特率差别不能超过10％
-Zilog Z8440 2000 kbit/s. Universal Synchronous/​Asynchronous Receiver/​Transmitter. Async, Bisync, SDLC, HDLC, X.25. CRC. 4-byte RX buffer. 2-byte TX buffer. Provides signals needed by a third party DMA controller to perform DMA transfers.[7] +
-Z8530/​Z85C30 This Universal Synchronous/​Asynchronous Receiver/​Transmitter has a 3 byte receive buffer and a 1 byte transmit buffer. It has hardware to accelerate the processing of HDLC and SDLC. The CMOS version (Z85C30) provides signals to allow a third party DMA controller to perform DMA transfers. It can do asynchronous,​ byte level synchronous,​ and bit level synchronous communications.[8] +
-8250 Obsolete with 1-byte buffers. These UARTs' maximum standard serial port speed is 9600 bits per second if the operating system has a 1 millisecond interrupt latency. 8250 UARTs were used in the IBM PC 5150 and IBM PC/XT, while the 16450 UART were used in IBM PC/​AT-series computers. +
-8251 +
-Motorola 6850 +
-6551 +
-Rockwell 65C52 +
-16450 +
-82510 This UART allows asynchronous operation up to 288 kbit/s, with two independent four-byte FIFOs. It was produced by Intel at least from 1993 to 1996, and Innovastic Semiconductor has a 2011 Data Sheet for IA82510. +
-16550 This UART's FIFO is broken, so it cannot safely run any faster than the 16450 UART. The 16550A and later versions fix this bug. +
-16550A This UART has 16-byte FIFO buffers. Its receive interrupt trigger levels can be set to 1, 4, 8, or 14 characters. Its maximum standard serial port speed if the operating system has a 1 millisecond interrupt latency is 115.2 kbit/s. Operating systems with lower interrupt latencies could handle higher baud rates like 230.4 kbit/s or 460.8 kbit/s. This chip can provide signals that are needed to allow a third party DMA controller to perform DMA transfers to and from the UART if the DMA mode this UART introduces is enabled.[9] It was introduced by National Semiconductor,​ which has been sold to Texas Instruments. National Semiconductor claimed that this UART could physically run at up to 1.5 Mbit/s. +
-16C552 +
-16650 This UART was introduced by Startech Semiconductor which is now owned by Exar Corporation and is not related to Startech.com. Early versions have a broken FIFO buffer and therefore cannot safely run any faster than the 16450 UART.[10] Versions of this UART that were not broken have 32-character FIFO buffers and could function at standard serial port speeds up to 230.4 kbit/s if the operating system has a 1 millisecond interrupt latency. Current versions of this UART by Exar claim to be able to physically handle up to 1.5 Mbit/s. This UART introduces the Auto-RTS and Auto-CTS features in which the RTS# signal is controlled by the UART to signal the external device to stop transmitting when the UART's buffer is full to or beyond a user-set trigger point and to stop transmitting to the device when the device drives the CTS# signal high (logic 0). +
-16750 64-byte buffers. This UART can handle a maximum standard serial port speed of 460.8 kbit/s if the maximum interrupt latency is 1 millisecond. This UART was introduced by Texas Instruments. TI claims that early models can run up to 1 Mbit/s physically, and later models can run up to 5 Mbit/s physically. +
-16850 128-byte buffers. This UART can handle a maximum standard serial port speed of 921.6 kbit/s if the maximum interrupt latency is 1 millisecond. This UART was introduced by Exar Corporation. Exar claims that early models can run up to 1.5 Mbit/s physically, and later models can run up to 6.25 Mbit/s physically. +
-16C850 +
-16950 128-byte buffers. This UART can handle a maximum standard serial port speed of 921.6 kbit/s if the maximum interrupt latency is 1 millisecond and if the UART is not connected to an enabled DMA controller. This UART supports ​9-bit characters in addition to the 5-8 bit characters that other UARTs support. This was introduced by Oxford Semiconductor,​ which is now owned by PLX Technology. Oxford/PLX claims that this UART can run up to 15 Mbit/s physically. PCI Express variants by Oxford/PLX can safely run much faster than other variants because they are integrated with a first party bus mastering PCIe DMA controller. This DMA controller is controlled by the UART's DMA mode signals that were defined for the 16550. The DMA controller will prevent buffer overruns by moving data in the receive buffer to the host computer'​s memory via PCIe, and can speed up transmission by moving data to be sent in the host computer'​s memory to the UART's transmit buffer if it is not full. Both of these operations do require some setup by the CPU, but are automated by the UART and the DMA controller after setup is complete. +
-16C950 +
-16954 Quad port version of the 16950/​16C950. 128-byte buffers per port. This UART can handle a maximum standard serial port speed of 921.6 kbit/s if the maximum interrupt latency is 1 millisecond and if the UART is not connected to an enabled DMA controller. This UART supports 9-bit characters in addition to the 5-8 bit characters that other UARTs support. This was introduced by Oxford Semiconductor,​ which is now owned by PLX Technology. Oxford/PLX claims that this UART can run up to 15 Mbit/s physically. PCI Express variants by Oxford/PLX can safely run much faster than other variants because they are integrated with a first party bus mastering PCIe DMA controller. This DMA controller is controlled by the UART's DMA mode signals that were defined for the 16550. The DMA controller will prevent buffer overruns by moving data in the receive buffer to the host computer'​s memory via PCIe, and can speed up transmission by moving data to be sent in the host computer'​s memory to the UART's transmit buffer if it is not full. Both of these operations do require some setup by the CPU, but are automated by the UART and the DMA controller after setup is complete. +
-16C954 +
-16C1550/​16C1551 UART with 16-byte FIFO buffers. Up to 1.5 Mbit/s. The ST16C155X is not compatible with the industry standard 16550 and will not work with the standard serial port driver in Microsoft Windows. +
-16C2450 Dual UART with 1-byte FIFO buffers. +
-16C2550 Dual UART with 16-byte FIFO buffers. Pin-to-pin and functional compatible to 16C2450. Software compatible with INS8250 and NS16C550. +
-SCC2691 Currently produced by NXP, the 2691 is a single channel UART that also includes a programmable counter/​timer. The 2691 has a single byte transmitter holding register and a 4-byte receive FIFO. Maximum standard speed of the 2692 is 115.2 kbit/s. Non-standard speeds are supported. +
-SCC2692 Currently produced by NXP, these dual UARTs (DUART) are essentially a pair of SCC2691 UARTs in a single package, but with a common counter/​timer. Each channel is independently programmable and supports independent transmit and receive data rates. Like the 2691, the 2692 has a single byte transmitter holding register and a 4-byte receive FIFO per channel. Maximum standard speed of both of the 2692's channels is 115.2 kbit/s. +
-The 26C92 is an upwardly compatible version of the dual channel 2692, with 8-byte transmit and receive FIFOs for improved performance during continuous bi-directional asynchronous transmission (CBAT) on both channels at the maximum standard speed of 230.4 kbit/s.+
  
-Both the 2692 and 26C92 may also be operated in RS-422 and RS-485 modes, and can also be programmed to support non-standard data rates. The devices are produced in PDIP-40, PLCC-44 and 44 pin QFP packages, and are readily adaptable to both Motorola and Intel buses. They have also been successfully adapted to the 65C02 and 65C816 buses.+实际应用中的信号传输方式 
 +将两个UART的设备进行连接有多种方式，取决于具体的应用场景，在这里我们仅看两种：TTL UART和RS-232。
  
-SC26C92 +TTL UART 
-SCC2698B Currently produced by NXP, the 2698 octal UART (OCTART) is essentially four SCC2692 DUARTs in a single package. Specifications are the same as the SCC2692 ​(not the SCC26C92). The device is produced in PDIP-64 and PLCC-84 packages, and is readily adaptable to both Motorola and Intel buses. The 2698 has also been successfully adapted to the 65C02 and 65C816 buses. +当微控制器和其它器件进行串行通信时，通常以TTL电平进行通信。 TTL串行信号存在于微控制器的电源电压范围内 - 通常为0V至3.3V或5V。 VCC电平（3.3V，5V等）的信号表示空闲线，值1或停止位。 0V（GND）信号表示起始位或值为0的数据位。 
-SCC28C94 Currently produced by NXP, the 28C94 quadruple ​UART (QUART) is functionally similar to a pair of SCC26C92 DUARTs mounted in a common package. Some additional signals are present for interrupt management and the auxiliary input/​output pins are arranged differently than those of the 26C92. Otherwise, the programming model for the 28C94 is very similar to that of the 26C92, requiring only minor code changes. The 28C94 supports a maximum standard speed of 230.4 kbit/s, is available in a PLCC-52 package, and is readily adaptable to both Motorola and Intel buses. + 
-SCC28L198 Currently produced by NXP, the 28L198 octal UART (OCTART) is essentially an up+{{ :​uart_ttl.jpg |}} 
 + 
 +RS-232 ​UART 
 + 
 +RS-232（推荐标准232）是连接数据终端设备（DTE）和数据通信设备（DCE）的串行二进制数据信号的标准。 它通常用于计算机的老式串口。 TTL电平UART和RS-232的主要区别就是电压电平。 RS-232中的数字信号为±3至 - ±15V，无论如何都不会检测到接近0V的信号。 
 + 
 +RS-232，可以在一些更古老的计算机和外围设备上找到，就像TTL串口翻转一样。 RS-232信号通常介于-13V和13V之间，但规格允许从+/​- 3V到+/- 25V。 在这些信号上，低电压（-5V，-13V等）表示空闲线，停止位或值为1的数据位。一个高的RS-232信号表示起始位或0- 值数据位。 这与TTL系列相反。 
 + 
 +^逻辑电平 |Logic-1 ​(High) | Logic-0 ​(Low) | 
 +^电压 ​   |+3 to +15v | -3 to -15v | 
 + 
 +{{ :uart_232.jpg |}} 
 + 
 +RS-232比TTL的UART有更多的引脚，用于PC和调制解调器之间的通信。 我们常用的DB-9的引脚排列及其功能如下所示。 
 +{{ :uaert_db9.jpg |}} 
 + 
 +{{ :​uart_signal.jpg |}} 
 + 
 +{{ :​uart_max232.png |}} 
 + 
 +最扑街的RS-232收发芯片 - MAX232 
 + 
 +在两个串行信号标准之间，TTL更容易实现到嵌入式电路中。 然而，低电压电平更容易受到长传输线路的损耗的影响。 RS-232或更复杂的标准（如RS-485）更适合远程串行传输。当您将两个串行设备连接在一起时，确保其信号电压匹配是非常重要的。  
 + 
 + 
 +### PC和微控制器的连接 
 + 
 +实际的项目中可以有多种方式来连接PC和MCU，最方便的是下面列出的几种方式中的最后一种。 
 + 
 + 
 +{{ :pcmcu1.jpg |}} 
 +TTL-UART到RS-232串口（古老的通用方式）  
 + 
 +{{ :pcmcu2.jpg |}} 
 +TTL-UART 到 RS-232串口 到 USB 
 + 
 +{{ :pcmcu3.jpg |}} 
 +USB-TTL 转换模块 
 + 
 + 
 +{{ :​esp8266_uart.jpg |}} 
 +全球创客界最火的WiFi模块ESP8266只需要UART接口和AT指令集进行操作 
 + 
 + 
 +{{ :cp2102modu.jpg |}} 
 + 
 +物美价廉的USB到TTL UART接口转换芯片CP2102（来自SiLabs），通过计算机的USB端口仿真UART通信 
 + 
 + 
 +### 使用UART最容易碰到的问题： 
 + 
 +#### RX-To-TX & TX-To-RX 
 + 
 +工程师经常犯的错误就是将RX和TX线错误连接，因此在遇到连接不通的时候一定要先检查确定一下是否存在这方面的问题。 
 +{{ :rx2tx2rx.jpg |}} 
 + 
 + 
 +#### 波特率失配 
 + 
 +如果数据以9600bps的波特率传输，并以19200bps的速率接收。 收到的数据将是一团垃圾！ 波特率必须在发送端和接收端匹配，这是UART串行通信的经验法则，波特率的最大允许偏移趋于介于（1-2％）之间。 因此尝试在两端生成完全相同的波特率，以避免错配错误。 
 +{{ :​baudrateerror.jpg |}} 
 + 
 +### UART总线长度 vs 波特率 
 +UART串行总线可以传输很长的距离，但传输的距离以及最高能够达到的波特率都取决于传输得越远，波特率也就会降低，它还取决于UART协议本身的硬件实现（物理层）。我们只提到TTL-UART和RS-232标准。 
 + 
 +#### RS-232 
 +RS-232的最大电缆长度为50英尺。 但实际上它取决于波特率、电缆的等效电容和环境噪声。 下表是TI多年前通过实验总结的一些经验法则。 
 +{{ :​baudlength.png |}} 
 + 
 +#### TTL-UART 
 + 
 +TTL电平的UART仅支持5V的电压摆幅，因此信号传输的距离以及能够支持到的波特率取决于下面的3个元素： 
 +  * 电缆的电阻 - 电缆越长电阻也就越高 
 +  * 电缆的电容：大家知道电容效应会阻碍信号电平的变化 
 +  * 噪声：任何环境中都会有噪声，带屏蔽的双绞线电缆对信号的传输会有帮助 
 + 
 +### UART的构成 
 +一个UART一般包含了如下的一些组成部分:​ 
 +  * 一个时钟发生器,​通常是比特率的整数倍，以便能够在一个bit周期的中间进行采样 
 +  * 输入和输出移位寄存器 
 +  * 发送/​接收控制 
 +  * 读/​写控制逻辑 
 +  * 发送/​接收缓存(可选) 
 +  * 系统数据总线缓存(可选) 
 +  * 先进先出(FIFO)缓存(可选) 
 +  * 第三方DMA控制器需要的信号(可选) 
 +  * 掌管DMA控制器的集成化总线(可选) 
 + 
 +### 用FPGA实现UART功能 
 +  - [[uart_verilog|UART的Verilog代码]] 
 +  - [[uart串口模块|基于STEP FPGA的UART串口通信模块驱动]]