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spi [2018/11/04 15:13]
gongyu [工作模式] 		spi [2018/11/05 07:45]
gongyu
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-SPI(Serial Peripheral Interface - 同步外设接口)总线是一种用于短距离通信（主要是嵌入式系统中）的同步串行通信接口规范，虽然没有正式的国际标准，但这种接口协议由Motorola发明迄今经过很多厂商的支持，已经成了一种事实标准，被广泛用于各种MCU处理器中，同传感器，串行ADC、DAC、存储器、SD卡以及LCD等进行数据连接。 +SPI(Serial Peripheral Interface - 同步外设接口)总线是一种用于短距离通信（主要是嵌入式系统中）的同步串行通信接口规范，虽然没有正式的国际标准，但这种接口协议由Motorola发明迄今经过很多厂商的支持，已经成了一种事实标准，被广泛用于各种[[MCU]]处理器中，同传感器，串行[[ADC]]、[[DAC]]、存储器、SD卡以及[[LCD]]等进行数据连接。 
-{{ :​spi_lpc.jpg |}}<WRAP centeralign>​ **当前的处理器中几乎都有SPI和I2C接口** </​WRAP>​+{{ :​spi_lpc.jpg |}}<WRAP centeralign>​ **当前的处理器中几乎都有[[SPI]]和[[I2C]]接口** </​WRAP>​
 {{ :​spi_sensor.jpg |}} <WRAP centeralign>​ 数字接口的传感器也采用SPI和I2C </​WRAP>​ {{ :​spi_sensor.jpg |}} <WRAP centeralign>​ 数字接口的传感器也采用SPI和I2C </​WRAP>​
 {{ :​spi_fpga.jpg |}} <WRAP centeralign>​ FPGA也将SPI、I2C硬化在器件内部方便各种外设的连接 </​WRAP>​ {{ :​spi_fpga.jpg |}} <WRAP centeralign>​ FPGA也将SPI、I2C硬化在器件内部方便各种外设的连接 </​WRAP>​
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 这种配置非常适合于主设备的信号引脚有限的场景。 这种配置非常适合于主设备的信号引脚有限的场景。
-===== 4种传输模式： =====+===== 4种传输模式 =====
 每次数据传输都是先将SSN（有的器件命名为SS，从选择线）被驱动为逻辑低电平时开始。由时钟的极性（CPOL）和相位（CPHA）构成了4种不同的数据传输模式（0,​1,​2,​3），分别对应四种可能的时钟配置。 每次数据传输都是先将SSN（有的器件命名为SS，从选择线）被驱动为逻辑低电平时开始。由时钟的极性（CPOL）和相位（CPHA）构成了4种不同的数据传输模式（0,​1,​2,​3），分别对应四种可能的时钟配置。
   * CPOL: 时钟的极性，它控制着时钟信号的初始逻辑状态。   * CPOL: 时钟的极性，它控制着时钟信号的初始逻辑状态。
   * CPHA: 时钟相位，它控制了数据转换和时钟转换之间的关系。   * CPHA: 时钟相位，它控制了数据转换和时钟转换之间的关系。
  
-To begin communication,​ the bus master configures the clock, using a frequency supported by the slave device, typically up to a few MHz. The master then selects the slave device with a logic level 0 on the select line. If a waiting period is required, such as for analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.+{{ :​400px-spi_timing_diagram2.svg.png|}} ​
  
-During each SPI clock cycle, a full duplex data transmission occurs. The master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it. This sequence is maintained even when only one-directional data transfer is intended.+具有非反相时钟极性（即，当从器件选择转换为逻辑低时，时钟处于逻辑低电平）： 
 +  * **模式0**：配置时钟相位使得数据在时钟脉冲的上升沿采样，并在时钟脉冲的下降沿移出。 这对应于上图中的第一个蓝色时钟轨迹。 请注意，数据必须在时钟的第一个上升沿之前可用。 
 +  * **模式1**：配置时钟相位使得数据在时钟脉冲的下降沿采样，并在时钟脉冲的上升沿移出。 这对应于上图中的第二个蓝色时钟轨迹。
  
-Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master and one in the slave; they are connected in a virtual ring topology. Data is usually shifted out with the most-significant bit first, while shifting a new less-significant bit into the same register. At the same time, Data from the counterpart is shifted into the least-significant bit register. After the register bits have been shifted out and in, the master and slave have exchanged register values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats. Transmission may continue for any number of clock cycles. When complete, the master stops toggling the clock signal, and typically deselects the slave.+使用反相时钟极性（即，当从器件选择转换为逻辑低时，时钟处于逻辑高电平）： 
 +  * **模式2**：配置时钟相位，使得数据在时钟脉冲的下降沿采样，并在时钟脉冲的上升沿移出。 这对应于上图中的第一个橙色时钟轨迹。 请注意，数据必须在时钟的第一个下降沿之前可用。 
 +  * **模式3**：配置时钟相位，使得数据在时钟脉冲的上升沿采样，并在时钟脉冲的下降沿移出。 这对应于上图中的第二个橙色时钟轨迹。
  
-Transmissions often consist of 8-bit words. However, other word sizes are also common, for example, 16-bit words for touchscreen controllers or audio codecs, such as the TSC2101 by Texas Instruments,​ or 12-bit words for many digital-to-analog or analog-to-digital converters.+由于主设备一般为可以编程各种模式的控制器/​处理器或者可以灵活编程的FPGA，因此在使用SPI连接的时候要认真阅读自己选用的从设备的工作模式，以便在时许上满足传输的要求。
  
-Every slave on the bus that has not been activated using its chip select line must disregard the input clock and MOSI signals, and must not drive MISO. 
  
-===时钟极性和相位=== +===== SPI数据传输的主设备端代码示例 ===== 
-{{ :​400px-spi_timing_diagram2.svg.png|}} A timing diagram showing clock polarity and phase. The red vertical line represents CPHA=0 and the blue vertical line represents ​CPHA=1 +以下是一段主设备工作于CPOL=0、CPHA=0模式时的数据传输的代码，每次传输为8位，此示例采用C语言。由于工作于CPOL=0， 在片选被选中之前要把时钟拉低，片选信号必须使能，也就是说在数据传输之前要将外设的片选信号电平变低，并在传输结束以后不再“使能”。 多数的外设允许或需要在片选信号选中以后进行多次传输，次子程序也许需要被多次调用。
-In addition to setting the clock frequency, the master must also configure the clock polarity and phase with respect to the data. Motorola SPI Block Guide[2] names these two options as CPOL and CPHA respectively,​ and most vendors have adopted that convention.+
  
-The timing diagram is shown to the right. The timing is further described below and applies to both the master and the slave device. +<​code ​c>
- +
-  * At CPOL=0 the base value of the clock is zero,i.e. the active state is 1 and idle state is 0. +
-    * For CPHA=0, data are captured on the clock'​s rising edge (low→high transition) and data is output on a falling edge (high→low clock transition). +
-    * For CPHA=1, data are captured on the clock'​s falling edge and data is output on a rising edge. +
-  * At CPOL=1 the base value of the clock is one (inversion of CPOL=0), i.e. the active state is 0 and idle state is 1. +
-    * For CPHA=0, data are captured on clock'​s falling edge and data is output on a rising edge. +
-    * For CPHA=1, data are captured on clock'​s rising edge and data is output on a falling edge. +
-That is, CPHA=0 means sampling on the first clock edge, while CPHA=1 means sampling on the second clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle. +
- +
-In other words, CPHA=0 means transmitting data on the active to idle state and CPHA=1 means that data is transmitted on the idle to active state edge. Note that if transmission happens on a particular edge, then capturing will happen on the opposite edge(i.e. if transmission happens on falling, then reception happens on rising and vice versa). The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle. +
- +
-This adds more flexibility to the communication channel between the master and slave. +
- +
-===模式编号=== +
-时钟两种极性和两种相位的组合形成了四种工作模式:​ +
-对于 "​Microchip PIC" / "​基于ARM的"​微控制器(注意NCPHA是CPHA反过来):​ +
- +
-^SPI模式 |时钟极性(CPOL/​CKP) ​  ​|时钟相位(CPHA) |时钟边沿(CKE/​NCPHA) | +
-^0 |0 |0 |1 ​  | +
-^1 |0 |1 |0 ​  | +
-^2 |1 |0 |1 ​  | +
-^3 |1 |1 |0 ​  | +
- +
-对于PIC32MX : SPI模式配置CKP,​CKE以及SMP位. 设置SMP位,​以及CKP,​CKE两位被配置为如上表中所示。 +
- +
-对于其它控制器:​ +
- +
-^SPI模式 |CPOL |CPHA ​ | +
-^0 |0 |0 ​    | +
-^1 |0 |1 ​    | +
-^2 |1 |0 ​    | +
-^3 |1 |1 ​    | +
- +
-=== 独立从设备配置 === +
-{{ :​350px-spi_three_slaves.svg.png |}} +
-<WRAP centeralign>​ 典型的SPI总线：1主和3个独立的从设备 </​WRAP>​ +
- +
-In the independent slave configuration,​ there is an independent chip select line for each slave. A pull-up resistor between power source and chip select line is highly recommended for each independent device to reduce cross-talk between devices. This is the way SPI is normally used. Since the MISO pins of the slaves are connected together, they are required to be tri-state pins (high, low or high-impedance). +
- +
-===Daisy chain configuration=== +
-{{ :​350px-spi_three_slaves_daisy_chained.svg.png|}} +
-Daisy-chained SPI bus: master and cooperative slaves +
-Some products that implement SPI may be connected in a daisy chain configuration,​ the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Such a feature only requires a single SS line from the master, rather than a separate SS line for each slave. +
- +
-Applications that require a daisy chain configuration include SGPIO and JTAG. +
- +
-===有效通信=== +
-Some slave devices are designed to ignore any SPI communications in which the number of clock pulses is greater than specified. Others do not care, ignoring extra inputs and continuing to shift the same output bit. It is common for different devices to use SPI communications with different lengths, as, for example, when SPI is used to access the scan chain of a digital IC by issuing a command word of one size (perhaps 32 bits) and then getting a response of a different size (perhaps 153 bits, one for each pin in that scan chain). +
- +
-===中断=== +
-SPI devices sometimes use another signal line to send an interrupt signal to a host CPU. Examples include pen-down interrupts from touchscreen sensors, thermal limit alerts from temperature sensors, alarms issued by real time clock chips, SDIO,[5] and headset jack insertions from the sound codec in a cell phone. Interrupts are not covered by the SPI standard; their usage is neither forbidden nor specified by the standard. +
- +
-===Example of bit-banging the master protocol=== +
-Below is an example of bit-banging the SPI protocol as an SPI master with CPOL=0, CPHA=0, and eight bits per transfer. The example is written in the C programming language. Because this is CPOL=0 the clock must be pulled low before the chip select is activated. The chip select line must be activated, which normally means being toggled low, for the peripheral before the start of the transfer, and then deactivated afterwards. Most peripherals allow or require several transfers while the select line is low; this routine might be called several times before deselecting the chip. +
-<​code ​java>+
 /* /*
  * Simultaneously transmit and receive a byte on the SPI.  * Simultaneously transmit and receive a byte on the SPI.
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 } }
 </​code>​ </​code>​
- +===== SPI的优点和缺点 ​===== 
-====优点和缺点==== +==== 优点 ​====
-===优点===+
   * 支持全双工通信   * 支持全双工通信
   * 推挽驱动(跟漏极开路正相反)提供了比较好的信号完整性和较高的速度   * 推挽驱动(跟漏极开路正相反)提供了比较好的信号完整性和较高的速度
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   * 对于时钟的速度没有上限，有进一步提高速度的潜力   * 对于时钟的速度没有上限，有进一步提高速度的潜力
  
-===缺点===+==== 缺点 ​====
   * 相比于I²C总线需要更多的管脚,​ 即便是只用到3根线的情况下   * 相比于I²C总线需要更多的管脚,​ 即便是只用到3根线的情况下
   * 没有寻址机制，在共享的总线连接时需要通过片选信号支持多个设备的访问   * 没有寻址机制，在共享的总线连接时需要通过片选信号支持多个设备的访问
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   * 有一些变种比如多路I/​O SPI和下面定义的三线串行总线都是半双工的   * 有一些变种比如多路I/​O SPI和下面定义的三线串行总线都是半双工的
  
-====应用====+===== 应用 ​=====
 The board real estate savings compared to a parallel I/O bus are significant,​ and have earned SPI a solid role in embedded systems. That is true for most system-on-a-chip processors, both with higher end 32-bit processors such as those using ARM, MIPS, or PowerPC and with other microcontrollers such as the AVR, PIC, and MSP430. These chips usually include SPI controllers capable of running in either master or slave mode. In-system programmable AVR controllers (including blank ones) can be programmed using an SPI interface. The board real estate savings compared to a parallel I/O bus are significant,​ and have earned SPI a solid role in embedded systems. That is true for most system-on-a-chip processors, both with higher end 32-bit processors such as those using ARM, MIPS, or PowerPC and with other microcontrollers such as the AVR, PIC, and MSP430. These chips usually include SPI controllers capable of running in either master or slave mode. In-system programmable AVR controllers (including blank ones) can be programmed using an SPI interface.
  
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   * LCD, sometimes even for managing image data   * LCD, sometimes even for managing image data
   * Any MMC or SD card (including SDIO variant[5])   * Any MMC or SD card (including SDIO variant[5])
 +
 For high performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based. For high performance systems, FPGAs sometimes use SPI to interface as a slave to a host, as a master to sensors, or for flash memory used to bootstrap if they are SRAM-based.
  
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 SGPIO is essentially another (incompatible) application stack for SPI designed for particular backplane management activities.[citation needed] SGPIO uses 3-bit messages. SGPIO is essentially another (incompatible) application stack for SPI designed for particular backplane management activities.[citation needed] SGPIO uses 3-bit messages.
  
-====标准====+===== 标准 ​=====
 SPI总线已经成了一种事实标准，然而却没有一个正式的标准，这就导致出现很多不同的协议选项，例如不同的Word大小；每个设备都有自己的协议定义，包括是否支持命令；有些设备只发送，其它的则只是接收；有的片选是高有效，有的则是低有效；有的协议先发送最低位。 SPI总线已经成了一种事实标准，然而却没有一个正式的标准，这就导致出现很多不同的协议选项，例如不同的Word大小；每个设备都有自己的协议定义，包括是否支持命令；有些设备只发送，其它的则只是接收；有的片选是高有效，有的则是低有效；有的协议先发送最低位。
- +===== 开发工具 ​=====
-Some devices even have minor variances from the CPOL/CPHA modes described above. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response. Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the chip select line. +
- +
-Some devices require an additional flow control signal from slave to master, indicating when data are ready. This leads to a 5-wire protocol instead of the usual 4. Such a ready or enable signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly,​ or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters do not support that signal directly, and instead rely on fixed delays.) +
- +
-Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the JTAG or SGPIO protocols, or any other protocol that requires messages that are not multiples of 8 bits. +
- +
-There are also hardware-level differences. Some chips combine MOSI and MISO into a single data line (SI/SO); this is sometimes called '​three-wire'​ signaling (in contrast to normal '​four-wire'​ SPI). Another variation of SPI removes the chip select line, managing protocol state machine entry/exit using other methods. Anyone needing an external connector for SPI defines their own: UEXT, JTAG connector, Secure Digital card socket, etc. Signal levels depend entirely on the chips involved. +
- +
-SafeSPI is an industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices. +
- +
-====开发工具====+
 When developing or troubleshooting systems using SPI, visibility at the level of hardware signals can be important. When developing or troubleshooting systems using SPI, visibility at the level of hardware signals can be important.
  
-===主适配卡===+==== 主适配卡 ​====
 There are a number of USB hardware solutions to provide computers, running Linux, Mac, or Windows, SPI master and/or slave capabilities. Many of them also provide scripting and/or programming capabilities (Visual Basic, C/C++, VHDL etc.). There are a number of USB hardware solutions to provide computers, running Linux, Mac, or Windows, SPI master and/or slave capabilities. Many of them also provide scripting and/or programming capabilities (Visual Basic, C/C++, VHDL etc.).
  
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 ^Dangerous Prototypes |Bus Pirate |USB |1-Wire,​ I2C, SPI, JTAG*, Asynchronous serial, Scriptable binary bitbang, UART |varies | ^Dangerous Prototypes |Bus Pirate |USB |1-Wire,​ I2C, SPI, JTAG*, Asynchronous serial, Scriptable binary bitbang, UART |varies |
  
-===协议分析仪===+====协议分析仪====
 SPI protocol analyzers are tools which sample an SPI bus and decode the electrical signals to provide a higher-level view of the data being transmitted on a specific bus. SPI protocol analyzers are tools which sample an SPI bus and decode the electrical signals to provide a higher-level view of the data being transmitted on a specific bus.
  
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 ^Total Phase |Promira Serial Platform |USB,​ Ethernet |eSPI |  ^Total Phase |Promira Serial Platform |USB,​ Ethernet |eSPI |
  
-===示波器===+==== 示波器 ​====
 Every major oscilloscope vendor offers oscilloscope-based triggering and protocol decoding for SPI. Most support 2-, 3-, and 4-wire SPI. The triggering and decoding capability is typically offered as an optional extra. SPI signals can be accessed via analog oscilloscope channels or with digital MSO channels.[9] Every major oscilloscope vendor offers oscilloscope-based triggering and protocol decoding for SPI. Most support 2-, 3-, and 4-wire SPI. The triggering and decoding capability is typically offered as an optional extra. SPI signals can be accessed via analog oscilloscope channels or with digital MSO channels.[9]
  
-===逻辑分析仪===+==== 逻辑分析仪 ​====
 When developing and/or troubleshooting the SPI bus, examination of hardware signals can be very important. Logic analyzers are tools which collect, analyze, decode, and store signals so people can view the high-speed waveforms at their leisure. Logic analyzers display time-stamps of each signal level change, which can help find protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data and show ASCII data. When developing and/or troubleshooting the SPI bus, examination of hardware signals can be very important. Logic analyzers are tools which collect, analyze, decode, and store signals so people can view the high-speed waveforms at their leisure. Logic analyzers display time-stamps of each signal level change, which can help find protocol problems. Most logic analyzers have the capability to decode bus signals into high-level protocol data and show ASCII data.
  
-====相关术语==== +=====相关术语===== 
-===Intelligent SPI controllers===+ 
 +====Intelligent SPI controllers====
 A queued serial peripheral interface (QSPI) is a type of SPI controller that uses a data queue to transfer data across the SPI bus.[10] It has a wrap-around mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently,​ the peripherals appear to the CPU as memory-mapped parallel devices. This feature is useful in applications such as control of an A/D converter. Other programmable features in QSPI are chip selects and transfer length/​delay. A queued serial peripheral interface (QSPI) is a type of SPI controller that uses a data queue to transfer data across the SPI bus.[10] It has a wrap-around mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently,​ the peripherals appear to the CPU as memory-mapped parallel devices. This feature is useful in applications such as control of an A/D converter. Other programmable features in QSPI are chip selects and transfer length/​delay.
  
 SPI controllers from different vendors support different feature sets; such DMA queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by multichannel buffered serial port (MCBSP).[11] Most SPI master controllers integrate support for up to four chip selects,​[12] although some require chip selects to be managed separately through GPIO lines. SPI controllers from different vendors support different feature sets; such DMA queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by multichannel buffered serial port (MCBSP).[11] Most SPI master controllers integrate support for up to four chip selects,​[12] although some require chip selects to be managed separately through GPIO lines.
  
-===Microwire===+====Microwire====
 Microwire, often spelled μWire, is essentially a predecessor of SPI and a trademark of National Semiconductor. It's a strict subset of SPI: half-duplex,​ and using SPI mode 0. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs. 20 MHz. Some Microwire chips also support a three-wire mode, which fits neatly with the restriction to half-duplex. Microwire, often spelled μWire, is essentially a predecessor of SPI and a trademark of National Semiconductor. It's a strict subset of SPI: half-duplex,​ and using SPI mode 0. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs. 20 MHz. Some Microwire chips also support a three-wire mode, which fits neatly with the restriction to half-duplex.
  
-===Microwire/​Plus===+====Microwire/​Plus====
 Microwire/​Plus is an enhancement of Microwire and features full-duplex communication and support for SPI modes 0 and 1. There was no specified improvement in serial clock speed. Microwire/​Plus is an enhancement of Microwire and features full-duplex communication and support for SPI modes 0 and 1. There was no specified improvement in serial clock speed.
  
-===Three-wire serial buses===+====Three-wire serial buses====
 As mentioned, one variant of SPI uses single bidirectional data line (slave out/slave in, called SISO) instead of two unidirectional ones (MOSI and MISO). This variant is restricted to a half duplex mode. It tends to be used for lower performance parts, such as small EEPROMs used only during system startup and certain sensors, and Microwire. Few SPI master controllers support this mode; although it can often be easily bit-banged in software. As mentioned, one variant of SPI uses single bidirectional data line (slave out/slave in, called SISO) instead of two unidirectional ones (MOSI and MISO). This variant is restricted to a half duplex mode. It tends to be used for lower performance parts, such as small EEPROMs used only during system startup and certain sensors, and Microwire. Few SPI master controllers support this mode; although it can often be easily bit-banged in software.
  
-===Multi I/O SPI===+====Multi I/O SPI====
 As opposed to three-wire serial buses, multi I/O SPI uses multiple parallel data lines (e.g., IO0 to IO3) to increase throughput. Dual I/O SPI using two data lines has comparable throughput to fast single I/O (MISO/​MOSI). Quad I/O SPI using four data lines has approximately double the throughput.[15] Multi I/O SPI devices tend to be half duplex similar to three-wire devices to avoid adding too many pins. These serial memory devices combine the advantage of more speed with reduced pin count as compared to parallel memory. As opposed to three-wire serial buses, multi I/O SPI uses multiple parallel data lines (e.g., IO0 to IO3) to increase throughput. Dual I/O SPI using two data lines has comparable throughput to fast single I/O (MISO/​MOSI). Quad I/O SPI using four data lines has approximately double the throughput.[15] Multi I/O SPI devices tend to be half duplex similar to three-wire devices to avoid adding too many pins. These serial memory devices combine the advantage of more speed with reduced pin count as compared to parallel memory.
  
-===mSPI===+====mSPI====
 {{ :​350px-mspi_three_slaves_svg.png|}} {{ :​350px-mspi_three_slaves_svg.png|}}
 Typical mSPI bus: master and three independent slaves Typical mSPI bus: master and three independent slaves
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 All slave devices share the same SS (Slave Select; active low) line, along with the other three SPI signals: SCLK, MOSI and MISO. Additionally all slave devices normally have their MISO line disconnected from the bus in a high impedance state. As in the standard SPI, begin of transmission is marked by the activation of the SS line low and the end is marked by its return to high. mSPI requires the bus master to issue a "slave address"​ (typically 8 bits) as mandatory first word in every transmission. Since all slave devices share the same SS line, the address word will be received by all of them at the same time. From that point further, only the device with the specified address will connect its MISO line to the bus and start communicating,​ while all other slave devices will ignore any data and wait for a new start of transmission and address. mSPI solves some of the basic disadvantages of the standard SPI at the expense of a slight decrease in the overall communication speed due to the initial addressing. All slave devices share the same SS (Slave Select; active low) line, along with the other three SPI signals: SCLK, MOSI and MISO. Additionally all slave devices normally have their MISO line disconnected from the bus in a high impedance state. As in the standard SPI, begin of transmission is marked by the activation of the SS line low and the end is marked by its return to high. mSPI requires the bus master to issue a "slave address"​ (typically 8 bits) as mandatory first word in every transmission. Since all slave devices share the same SS line, the address word will be received by all of them at the same time. From that point further, only the device with the specified address will connect its MISO line to the bus and start communicating,​ while all other slave devices will ignore any data and wait for a new start of transmission and address. mSPI solves some of the basic disadvantages of the standard SPI at the expense of a slight decrease in the overall communication speed due to the initial addressing.
  
-===Intel Enhanced Serial Peripheral Interface Bus===+====Intel Enhanced Serial Peripheral Interface Bus====
 Intel has developed a successor to its Low Pin Count (LPC) bus that it calls the Enhanced Serial Peripheral Interface Bus, or eSPI for short. Intel aims to allow the reduction in the number of pins required on motherboards compared to systems using LPC, have more available throughput than LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals),​ tunnel previous out-of-band pins through the eSPI bus, and allow system designers to trade off cost and performance.[16] Intel has developed a successor to its Low Pin Count (LPC) bus that it calls the Enhanced Serial Peripheral Interface Bus, or eSPI for short. Intel aims to allow the reduction in the number of pins required on motherboards compared to systems using LPC, have more available throughput than LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals),​ tunnel previous out-of-band pins through the eSPI bus, and allow system designers to trade off cost and performance.[16]