序列检测测试文件
// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Module: Serial_Detect_test
//
// Author: Step
//
// Description: Testbench for Serial_Detect
//
// Web: www.ecbcamp.com
//
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Version: |Mod. Date: |Changes Made:
// V1.0 |2015/11/11 |Initial ver
// --------------------------------------------------------------------
`timescale 1ns / 100ps
module Serial_Detect_test;
parameter CLK_PERIOD = 40; //CLK_PERIOD=40ns, Frequency=25MHz
parameter CNT_NUM = 5;
reg sys_clk;
initial
sys_clk = 1'b0;
always
sys_clk = #(CLK_PERIOD/2) ~sys_clk;
reg sys_rst_n; //active low
initial
begin
sys_rst_n = 1'b0;
#100;
sys_rst_n = 1'b1;
end
reg vin;
always vin = # 400 $random;
wire clk_1hz,vout;
Serial_Detect #
(
.CNT_NUM(CNT_NUM)
)
Serial_Detect_uut
(
.clk(sys_clk),
.rst_n(sys_rst_n),
.vin(vin),
.clk_1hz(clk_1hz),
.vout(vout)
);
endmodule