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rs-232 [2017/03/26 19:51] gongyu [接收器] |
rs-232 [2017/03/26 20:00] (当前版本) gongyu [应用案例] |
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====== 应用案例 ====== | ====== 应用案例 ====== | ||
+ | This design allows controlling a few FPGA pins from your PC (through your PC's serial port). | ||
+ | |||
+ | * It create 8 outputs on the FPGA (port named "GPout"). GPout is updated by any character that the FPGA receives. | ||
+ | * Also 8 inputs on the FPGA (port named "GPin"). GPin is transmitted every time the FPGA receives a character. | ||
+ | |||
+ | The GP outputs can be used to control anything remotely from your PC, might be LEDs or a coffee machine... | ||
+ | <code verilog> | ||
+ | module serialGPIO( | ||
+ | input clk, | ||
+ | input RxD, | ||
+ | output TxD, | ||
+ | |||
+ | output reg [7:0] GPout, // general purpose outputs | ||
+ | input [7:0] GPin // general purpose inputs | ||
+ | ); | ||
+ | |||
+ | wire RxD_data_ready; | ||
+ | wire [7:0] RxD_data; | ||
+ | async_receiver RX(.clk(clk), .RxD(RxD), .RxD_data_ready(RxD_data_ready), .RxD_data(RxD_data)); | ||
+ | always @(posedge clk) if(RxD_data_ready) GPout <= RxD_data; | ||
+ | |||
+ | async_transmitter TX(.clk(clk), .TxD(TxD), .TxD_start(RxD_data_ready), .TxD_data(GPin)); | ||
+ | endmodule | ||
+ | |||
+ | </code> | ||
+ | |||
+ | Remember to grab the async_receiver and async_transmitter modules here, and to update the clock frequency values inside. |