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后一修订版 | 前一修订版 | ||
lightness.v [2016/06/27 09:06] anran 创建 |
lightness.v [2016/06/29 16:23] (当前版本) anran |
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module Lightness | module Lightness | ||
( | ( | ||
- | input clk_in, | + | input clk_in, |
- | input rst_n_in, | + | input rst_n_in, |
- | input up_pulse, | + | input [2:0] color, |
- | input down_pulse, | + | input up_pulse, |
- | output reg Lightness_out | + | input down_pulse, |
+ | output reg Lightness_out | ||
); | ); | ||
- | localparam CYCLE = 10; | + | localparam CYCLE_ONE = 5; |
+ | localparam CYCLE_TWO = 10; | ||
+ | localparam CYCLE_THREE = 15; | ||
+ | |||
+ | reg [3:0] cycle; | ||
+ | //Control duty cycle | ||
+ | always @(color) begin | ||
+ | case(color) | ||
+ | 3'b110: cycle = CYCLE_ONE; | ||
+ | 3'b101: cycle = CYCLE_ONE; | ||
+ | 3'b011: cycle = CYCLE_ONE; | ||
+ | 3'b100: cycle = CYCLE_TWO; | ||
+ | 3'b010: cycle = CYCLE_TWO; | ||
+ | 3'b001: cycle = CYCLE_TWO; | ||
+ | 3'b000: cycle = CYCLE_THREE; | ||
+ | 3'b111: cycle = CYCLE_THREE; | ||
+ | default: cycle = CYCLE_ONE; | ||
+ | endcase | ||
+ | end | ||
reg [3:0] duty; | reg [3:0] duty; | ||
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always @(posedge clk_in or negedge rst_n_in) begin | always @(posedge clk_in or negedge rst_n_in) begin | ||
if(!rst_n_in) begin | if(!rst_n_in) begin | ||
- | duty<=4'd5; | + | duty<=4'd2; |
end else begin | end else begin | ||
- | if(up_pulse && (duty<CYCLE)) duty <= duty + 4'd1; | + | if(up_pulse && (duty<CYCLE_ONE)) duty <= duty + 4'd1; |
else if(down_pulse && (duty>4'd0)) duty <= duty - 4'd1; | else if(down_pulse && (duty>4'd0)) duty <= duty - 4'd1; | ||
else duty <= duty; | else duty <= duty; | ||
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cnt<=4'd0; | cnt<=4'd0; | ||
end else begin | end else begin | ||
- | if(cnt>=CYCLE) cnt<=4'd0; | + | if(cnt>=cycle) cnt<=4'd0; |
else cnt <= cnt + 4'd1; | else cnt <= cnt + 4'd1; | ||
end | end | ||
行 64: | 行 83: | ||
endmodule | endmodule | ||
- | |||
</code> | </code> |