差别
这里会显示出您选择的修订版和当前版本之间的差别。
| 上一修订版 两侧同时换到之后的修订记录 | |||
|
hb_led [2021/09/13 01:58] gongyu 创建 |
hb_led [2021/10/21 21:35] gongyu [5. 代码设计] |
||
|---|---|---|---|
| 行 38: | 行 38: | ||
| ### 5. 代码设计 | ### 5. 代码设计 | ||
| + | |||
| + | <code verilog> | ||
| + | module LEDblink(clk, LED); | ||
| + | input clk; // clock typically from 10MHz to 50MHz | ||
| + | output LED; | ||
| + | |||
| + | // create a binary counter | ||
| + | reg [31:0] cnt; | ||
| + | always @(posedge clk) cnt <= cnt+1; | ||
| + | |||
| + | assign LED = cnt[22]; // blink the LED at a few Hz (using the 23th bit of the counter, use a different bit to modify the blinking rate) | ||
| + | endmodule | ||
| + | |||
| + | </code> | ||
| #### 5.1 设计文件 | #### 5.1 设计文件 | ||