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在电赛训练板上实现DDS的功能
关于用FPGA实现DDS的过程可以参考文档：DDS生成任意波形的方法及Verilog代码实例
顶层模块
module top(clk_in,sys_rst_n,key_a,key_b,key_ok,dac_data,dac_clk,oled_rst,oled_dcn,oled_clk,oled_dat); input clk_in,sys_rst_n,key_a,key_b,key_ok; //input [3:0] sw; output [9:0] dac_data; output dac_clk; output oled_rst; output oled_dcn; output oled_clk; output oled_dat; wire L_pulse,R_pulse,O_pulse; wire clk120,clk60,clk96; wire locked; wire rst_n; assign led=8'hff; assign rgbled=6'b111111; wire [1:0] wave; wire [26:0] WaveFreq; OLED12864 OLED12864_u1 ( .clk (clk_in) , .rst_n (rst_n), //.sw (cnt_seg), .wave (wave), //.oled_csn(oled_csn), .WaveFreq(WaveFreq), .oled_rst(oled_rst), .oled_dcn(oled_dcn), .oled_clk(oled_clk), .oled_dat(oled_dat) ); assign dac_clk=clk120; dds dds_u( .clk_in (clk120) , .rst_n (rst_n) , .O_pulse (O_pulse) , .L_pulse (L_pulse) , .R_pulse (R_pulse) , .dac_data(dac_data) , .wave (wave), .WaveFreq(WaveFreq) );// assign rst_n=sys_rst_n&locked; pll1 pll1_inst ( .areset ( ~sys_rst_n ), .inclk0 ( clk_in ), .c0 ( clk120 ), .locked ( locked ) ); Encoder Encoder_u( .clk_in (clk120), .rst_n_in (rst_n), .key_a (key_a), .key_b (key_b), .key_ok (key_ok), .Left_pulse (L_pulse), .Right_pulse(R_pulse), .OK_pulse (O_pulse) ); endmodule
DDS核心模块
这是DDS的主代码，可以选择输出的波形以及相应的频率
// -------------------------------------------------------------------- // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // -------------------------------------------------------------------- // Module: dds // // Author: Step // // Description: dds // // Web: www.stepfapga.com // // -------------------------------------------------------------------- // Code Revision History : // -------------------------------------------------------------------- // Version: |Mod. Date: |Changes Made: // V1.0 |2021.11.27 |Initial ver // -------------------------------------------------------------------- module dds(clk_in,rst_n,O_pulse,L_pulse,R_pulse,dac_data,wave,WaveFreq);// localparam SIN = 2'b00, SAW = 2'b01, TRI = 2'b10, SQU = 2'b11; input clk_in; // 小脚丫FPGA的外部时钟频率为12MHz input rst_n; input wire O_pulse,L_pulse,R_pulse; output reg [9:0] dac_data; // 10位数据输出送给外部的DAC output reg [1:0] wave; output reg [26:0] WaveFreq; reg [23:0] phase_acc; //增加相位累加器位数使得分辨率提高 wire [23:0] phase; reg [23:0] f_inc; assign phase=phase_acc; always @(posedge clk_in) phase_acc <= phase_acc + f_inc; //f_inc=24'd27962;主时钟为12MHz，则产生20KHz的正弦波信号 wire [9:0] sin_dat; //正弦波 wire [9:0] saw_dat = phase[23:14]; //锯齿波 wire [9:0] tri_dat = phase[23]? (~phase[22:13]) : phase[22:13]; //三角波 wire [9:0] squ_dat = phase[23]? 10'h3ff : 10'h000; //方波 always @(*) begin case(wave) 2'b00: dac_data = sin_dat; //正弦波 2'b01: dac_data = saw_dat; //锯齿波 2'b10: dac_data = tri_dat; //三角波 2'b11: dac_data = squ_dat; //方波 default: dac_data = sin_dat; //正弦波 endcase end lookup_tables u_lookup_tables(.phase(phase_acc[23:16]), .sin_out(sin_dat)); //波形输出选择 always @(posedge clk_in or negedge rst_n) begin if(!rst_n) wave <= SIN; else if(O_pulse)begin case(wave) SIN: wave <= SAW; SAW: wave <= TRI; TRI: wave <= SQU; SQU: wave <= SIN; default: wave <= SIN; endcase end else wave <= wave; end //频率控制 always@(posedge clk_in or negedge rst_n) begin if(!rst_n) begin f_inc <= 24'h22222; WaveFreq<=1_000_000; end else if(L_pulse==1'b1) begin if(f_inc <= 24'h369d) f_inc <= f_inc; else begin f_inc <= f_inc - 24'h369d; WaveFreq<=WaveFreq-100000; end end else if(R_pulse==1'b1) begin if(f_inc >= 24'h155554) f_inc <= f_inc; else begin f_inc <= f_inc + 24'h369d; WaveFreq<=WaveFreq+100000; end end else f_inc <= f_inc; end endmodule //dds时钟频率给定后，输出信号的频率取决于频率控制字， // 频率分辨率取决于累加器位数， // 相位分辨率取决于ROM的地址线位数， // 幅度量化噪声取决于ROM的数据位字长和D/A转换器位数
查找表的程序，主要是利用了正弦波的对称性，为了节省FPGA的资源，可以只构建一个象限的波形，另外3个象限可以基于其对称性通过逻辑来实现。
/* lookup_tables.v */ module lookup_tables(phase, sin_out); input [7:0] phase; output [9:0] sin_out; wire [9:0] sin_out; reg [5:0] address; wire [1:0] sel; wire [8:0] sine_table_out; reg [9:0] sine_onecycle_amp; //assign sin_out = {4'b0, sine_onecycle_amp[9:4]} + 9'hff; // 可以调节输出信号的幅度 assign sin_out = sine_onecycle_amp[9:0]; assign sel = phase[7:6]; sin_table u_sin_table(address,sine_table_out); always @(sel or sine_table_out) begin case(sel) 2'b00: begin sine_onecycle_amp = 9'h1ff + sine_table_out[8:0]; address = phase[5:0]; end 2'b01: begin sine_onecycle_amp = 9'h1ff + sine_table_out[8:0]; address = ~phase[5:0]; end 2'b10: begin sine_onecycle_amp = 9'h1ff - sine_table_out[8:0]; address = phase[5:0]; end 2'b11: begin sine_onecycle_amp = 9'h1ff - sine_table_out[8:0]; address = ~ phase[5:0]; end endcase end endmodule
构建正弦波表的程序，Lattice的Diamond以及Inel的Quartus编译工具中都有相应的IP可以直接调用使用。
module sin_table(address,sin); output [8:0] sin; input [5:0] address; reg [8:0] sin; always @(address) begin case(address) 6'h0: sin=9'h0; 6'h1: sin=9'hC; 6'h2: sin=9'h19; 6'h3: sin=9'h25; 6'h4: sin=9'h32; 6'h5: sin=9'h3E; 6'h6: sin=9'h4B; 6'h7: sin=9'h57; 6'h8: sin=9'h63; 6'h9: sin=9'h70; 6'ha: sin=9'h7C; 6'hb: sin=9'h88; 6'hc: sin=9'h94; 6'hd: sin=9'hA0; 6'he: sin=9'hAC; 6'hf: sin=9'hB8; 6'h10: sin=9'hC3; 6'h11: sin=9'hCF; 6'h12: sin=9'hDA; 6'h13: sin=9'hE6; 6'h14: sin=9'hF1; 6'h15: sin=9'hFC; 6'h16: sin=9'h107; 6'h17: sin=9'h111; 6'h18: sin=9'h11C; 6'h19: sin=9'h126; 6'h1a: sin=9'h130; 6'h1b: sin=9'h13A; 6'h1c: sin=9'h144; 6'h1d: sin=9'h14E; 6'h1e: sin=9'h157; 6'h1f: sin=9'h161; 6'h20: sin=9'h16A; 6'h21: sin=9'h172; 6'h22: sin=9'h17B; 6'h23: sin=9'h183; 6'h24: sin=9'h18B; 6'h25: sin=9'h193; 6'h26: sin=9'h19B; 6'h27: sin=9'h1A2; 6'h28: sin=9'h1A9; 6'h29: sin=9'h1B0; 6'h2a: sin=9'h1B7; 6'h2b: sin=9'h1BD; 6'h2c: sin=9'h1C3; 6'h2d: sin=9'h1C9; 6'h2e: sin=9'h1CE; 6'h2f: sin=9'h1D4; 6'h30: sin=9'h1D9; 6'h31: sin=9'h1DD; 6'h32: sin=9'h1E2; 6'h33: sin=9'h1E6; 6'h34: sin=9'h1E9; 6'h35: sin=9'h1ED; 6'h36: sin=9'h1F0; 6'h37: sin=9'h1F3; 6'h38: sin=9'h1F6; 6'h39: sin=9'h1F8; 6'h3a: sin=9'h1FA; 6'h3b: sin=9'h1FC; 6'h3c: sin=9'h1FD; 6'h3d: sin=9'h1FE; 6'h3e: sin=9'h1FF; 6'h3f: sin=9'h1FF; endcase end endmodule
编码器输入模块
// -------------------------------------------------------------------- // >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // -------------------------------------------------------------------- // Module: Encoder // // Author: Step // // Description: Driver for rotary encoder // // Web: www.stepfapga.com // // -------------------------------------------------------------------- // Code Revision History : // -------------------------------------------------------------------- // Version: |Mod. Date: |Changes Made: // V1.0 |2021.11.27 |Initial ver // -------------------------------------------------------------------- module Encoder ( input clk_in, //系统时钟 input rst_n_in, //系统复位，低有效 input wire key_a, input wire key_b, input wire key_ok, output reg Left_pulse, //左旋转脉冲输出 output reg Right_pulse, //右旋转脉冲输出 output OK_pulse //按动脉冲输出 ); localparam NUM_500US = 6_0000; reg [15:0] cnt; //计数器周期为500us，控制键值采样频率 always@(posedge clk_in or negedge rst_n_in) begin if(!rst_n_in) cnt <= 0; else if(cnt >= NUM_500US-1) cnt <= 1'b0; else cnt <= cnt + 1'b1; end reg [5:0] cnt_20ms; reg key_a_r,key_a_r1; reg key_b_r,key_b_r1; reg key_ok_r; //针对A、B、D管脚分别做简单去抖操作， //如果对旋转编码器的要求比较高，建议现对旋转编码器的输出做严格的消抖处理后再来做旋转编码器的驱动 //对旋转编码器的输入缓存，消除亚稳态同时延时锁存 always@(posedge clk_in or negedge rst_n_in) begin if(!rst_n_in) begin key_a_r <= 1'b1; key_a_r1 <= 1'b1; key_b_r <= 1'b1; key_b_r1 <= 1'b1; cnt_20ms <= 1'b1; key_ok_r <= 1'b1; end else if(cnt == NUM_500US-1) begin key_a_r <= key_a; key_a_r1 <= key_a_r; key_b_r <= key_b; key_b_r1 <= key_b_r; if(cnt_20ms >= 6'd40) begin //对于按键D信号还是采用20ms周期采样的方法，40*500us = 20ms cnt_20ms <= 6'd0; key_ok_r <= key_ok; end else begin cnt_20ms <= cnt_20ms + 1'b1; key_ok_r <= key_ok_r; end end end reg key_ok_r1; //对按键D信号进行延时锁存 always@(posedge clk_in or negedge rst_n_in) begin if(!rst_n_in) key_ok_r1 <= 1'b1; else key_ok_r1 <= key_ok_r; end wire A_state = key_a_r1 && key_a_r && key_a; //旋转编码器A信号高电平状态检测 wire B_state = key_b_r1 && key_b_r && key_b; //旋转编码器B信号高电平状态检测 assign OK_pulse = key_ok_r1 && (!key_ok_r); //旋转编码器D信号下降沿检测 reg A_state_reg; //延时锁存 always@(posedge clk_in or negedge rst_n_in) begin if(!rst_n_in) A_state_reg <= 1'b1; else A_state_reg <= A_state; end //旋转编码器A信号的上升沿和下降沿检测 wire A_pos = (!A_state_reg) && A_state; wire A_neg = A_state_reg && (!A_state); //通过旋转编码器A信号的边沿和B信号的电平状态的组合判断旋转编码器的操作，并输出对应的脉冲信号 always@(posedge clk_in or negedge rst_n_in)begin if(!rst_n_in)begin Right_pulse <= 1'b0; Left_pulse <= 1'b0; end else begin if(A_pos && B_state) Left_pulse <= 1'b1; else if(A_neg && B_state) Right_pulse <= 1'b1; else begin Right_pulse <= 1'b0; Left_pulse <= 1'b0; end end end endmodule
OLED显示模块
这是通过SPI总线方式来驱动12864分辨率的OLED显示屏显示相应信息的逻辑代码
<code verilog>
——————————————————————–
Module: OLED12864
Description: OLED12864Driver锛屼娇鐢8鐐归樀瀛楀簱锛屾瘡琛屾樉绀28/8=16涓瓧绗
——————————————————————–
module OLED12864
(
input clk, 12MHz绯荤粺鏃堕挓
input rstn, 绯荤粺澶嶄綅锛屼綆鏈夋晥
input [3:0] sw,
input [1:0] wave,
input [26:0] WaveFreq,
output reg oledcsn, OLCD娑叉櫠灞忎娇鑳
output reg oledrst, OLCD娑叉櫠灞忓浣
output reg oleddcn, OLCD鏁版嵁鎸囦护鎺у埗
output reg oledclk, OLCD鏃堕挓淇″彿
output reg oleddat OLCD鏁版嵁淇″彿
);
localparam INITDEPTH = 16'd23; LCD鍒濆鍖栫殑鍛戒护鐨勬暟閲
localparam IDLE = 7'h1, MAIN = 7'h2, INIT = 7'h4, SCAN = 7'h8, WRITE = 7'h10, DELAY = 7'h20,CHINESE=7'h40;
localparam HIGH = 1'b1, LOW = 1'b0;
localparam DATA = 1'b1, CMD = 1'b0;
reg [7:0] cmd [24:0];
reg [39:0] mem [122:0];
reg [63:0] memhanzi[79:0];
reg [4:0] lengthhanzi;
reg [7:0] yp, xph, xpl;
reg [(821-1):0] char;
reg [7:0] num, charreg;
reg [4:0] cntmain, cntinit, cntscan, cntwrite,cntchinese;
reg [15:0] numdelay, cntdelay, cnt;
reg [6:0] state, stateback;
reg [4:0] hanzifuzhujishu;
wire [(816-1):0] char3;
getChar3 getChar3 (
.clk(clk),
.rstn(rstn),
.WaveFreq(WaveFreq),
.char(char3)
);
always @ (posedge clk or negedge rstn) begin
if(!rstn) begin
cntmain ⇐ 1'b0; cntinit ⇐ 1'b0; cntscan ⇐ 1'b0; cntwrite ⇐ 1'b0;cntchinese ⇐ 1'b0;
yp ⇐ 1'b0; xph ⇐ 1'b0; xpl ⇐ 1'b0;lengthhanzi⇐5'd0;hanzifuzhujishu⇐5'd0;
num ⇐ 1'b0; char ⇐ 1'b0; charreg ⇐ 1'b0;
numdelay ⇐ 16'd5; cntdelay ⇐ 1'b0; cnt ⇐ 1'b0;
oledcsn ⇐ HIGH; oledrst ⇐ HIGH; oleddcn ⇐ CMD; oledclk ⇐ HIGH; oleddat ⇐ LOW;
state ⇐ IDLE; stateback ⇐ IDLE;
end else begin
case(state)
IDLE:begin
cntmain ⇐ 1'b0; cntinit ⇐ 1'b0; cntscan ⇐ 1'b0; cntwrite ⇐ 1'b0;
yp ⇐ 1'b0; xph ⇐ 1'b0; xpl ⇐ 1'b0;
num ⇐ 1'b0; char ⇐ 1'b0; charreg ⇐ 1'b0;
numdelay ⇐ 16'd5; cntdelay ⇐ 1'b0; cnt ⇐ 1'b0;
oledcsn ⇐ HIGH; oledrst ⇐ HIGH; oleddcn ⇐ CMD; oledclk ⇐ HIGH; oleddat ⇐ LOW;
state ⇐ MAIN; stateback ⇐ MAIN;
end
MAIN:begin
if(cntmain >= 5'd14) cntmain ⇐ 5'd12;
else cntmain ⇐ cntmain + 1'b1;
case(cntmain) MAIN鐘舵€
5'd0 : begin state ⇐ INIT; end
5'd1 : begin yp ⇐ 8'hb0; xph ⇐ 8'h10; xpl ⇐ 8'h00; num ⇐ 5'd8; char ⇐ “DDS ”;state ⇐ SCAN; end
5'd2 : begin yp ⇐ 8'hb1; xph ⇐ 8'h10; xpl ⇐ 8'h00; num ⇐ 5'd8; char ⇐ “ ”;state ⇐ SCAN; end
5'd3 : begin yp ⇐ 8'hb0; xph ⇐ 8'h14; xpl ⇐ 8'h00; num ⇐ 5'd8; char ⇐ “ ”;state ⇐ SCAN; end
5'd4 : begin yp ⇐ 8'hb1; xph ⇐ 8'h14; xpl ⇐ 8'h00; num ⇐ 5'd8; char ⇐ “ ”;state ⇐ SCAN; end
5'd5 : begin yp ⇐ 8'hb2; xph ⇐ 8'h14; xpl ⇐ 8'h00; num ⇐ 5'd8; char ⇐ “ ”;state ⇐ SCAN; end
5'd6 : begin yp ⇐ 8'hb3; xph ⇐ 8'h14; xpl ⇐ 8'h00; num ⇐ 5'd8; char ⇐ “ ”;state ⇐ SCAN; end
5'd7 : begin yp ⇐ 8'hb4; xph ⇐ 8'h10; xpl ⇐ 8'h00; num ⇐ 5'd16; char ⇐ “ ”;state ⇐ SCAN; end
5'd8 : begin yp ⇐ 8'hb5; xph ⇐ 8'h10; xpl ⇐ 8'h00; num ⇐ 5'd16; char ⇐ “ ”;state ⇐ SCAN; end
5'd9 : begin yp ⇐ 8'hb6; xph ⇐ 8'h10; xpl ⇐ 8'h00; num ⇐ 5'd16; char ⇐ “ ”;state ⇐ SCAN; end
5'd10: begin yp ⇐ 8'hb7; xph ⇐ 8'h10; xpl ⇐ 8'h00; num ⇐ 5'd16; char ⇐ “ ”;state ⇐ SCAN; end
5'd11: ;begin yp ⇐ 8'hb1; xph ⇐ 8'h15; xpl ⇐ 8'h00; num ⇐ 5'd 1; char ⇐ sw; state ⇐ SCAN; end
5'd12: begin yp ⇐ 8'hb2; xph ⇐ 8'h10; xpl ⇐ 8'h00; lengthhanzi ⇐ 5'd9;
if (wave==2'b00)begin hanzifuzhujishu⇐5'd8;state ⇐ CHINESE; end
else if(wave==2'b01)begin hanzifuzhujishu⇐5'd2;state ⇐ CHINESE; end
else if(wave==2'b10)begin hanzifuzhujishu⇐5'd4;state ⇐ CHINESE; end
else begin hanzifuzhujishu⇐5'd6;state ⇐ CHINESE; end if(wave==2'b11)
end
5'd13 : begin yp ⇐ 8'hb3; xph ⇐ 8'h10; xpl ⇐ 8'h00; lengthhanzi ⇐ 5'd9;
if (wave==2'b00)begin hanzifuzhujishu⇐5'd9;state ⇐ CHINESE; end
else if(wave==2'b01)begin hanzifuzhujishu⇐5'd3;state ⇐ CHINESE; end
else if(wave==2'b10)begin hanzifuzhujishu⇐5'd5;state ⇐ CHINESE; end
else begin hanzifuzhujishu⇐5'd7;state ⇐ CHINESE; end if(wave==2'b11)
end
5'd14 : begin yp ⇐ 8'hb5; xph ⇐ 8'h10; xpl ⇐ 8'h00; num ⇐ 5'd16; char ⇐ char3;state ⇐ SCAN; end
default: state ⇐ IDLE;
endcase
end
INIT:begin 鍒濆鍖栫姸鎬
case(cntinit)
5'd0: begin oledrst ⇐ LOW; cntinit ⇐ cntinit + 1'b1; end 澶嶄綅鏈夋晥
5'd1: begin numdelay ⇐ 16'd25000; state ⇐ DELAY; stateback ⇐ INIT; cntinit ⇐ cntinit + 1'b1; end 寤舵椂澶т簬3us
5'd2: begin oledrst ⇐ HIGH; cntinit ⇐ cntinit + 1'b1; end 澶嶄綅鎭㈠
5'd3: begin numdelay ⇐ 16'd25000; state ⇐ DELAY; stateback ⇐ INIT; cntinit ⇐ cntinit + 1'b1; end 寤舵椂澶т簬220us
5'd4: begin
if(cnt>=INITDEPTH) begin 褰5鏉℃寚浠ゅ強鏁版嵁鍙戝嚭鍚庯紝閰嶇疆瀹屾垚
cnt ⇐ 1'b0;
cntinit ⇐ cntinit + 1'b1;
end else begin
cnt ⇐ cnt + 1'b1; numdelay ⇐ 16'd5;
oleddcn ⇐ CMD; charreg ⇐ cmd[cnt]; state ⇐ WRITE; stateback ⇐ INIT;
end
end
5'd5: begin cntinit ⇐ 1'b0; state ⇐ MAIN; end 鍒濆鍖栧畬鎴愶紝杩斿洖MAIN鐘舵€
default: state ⇐ IDLE;
endcase
end
SCAN:begin 鍒峰睆鐘舵€侊紝浠嶳AM涓鍙栨暟鎹埛灞
if(cntscan == 5'd11) begin
if(num) cntscan ⇐ 5'd3;
else cntscan ⇐ cntscan + 1'b1;
end
else if(cntscan == 5'd12) cntscan ⇐ 1'b0;
else cntscan ⇐ cntscan + 1'b1;
case(cntscan)
5'd 0: begin oleddcn ⇐ CMD; charreg ⇐ yp; state ⇐ WRITE; stateback ⇐ SCAN; end 瀹氫綅鍒楅〉鍦板潃
5'd 1: begin oleddcn ⇐ CMD; charreg ⇐ xpl; state ⇐ WRITE; stateback ⇐ SCAN; end 瀹氫綅琛屽湴鍧€浣庝綅
5'd 2: begin oleddcn ⇐ CMD; charreg ⇐ xph; state ⇐ WRITE; stateback ⇐ SCAN; end 瀹氫綅琛屽湴鍧€楂樹綅
5'd 3: begin num ⇐ num - 1'b1;end
5'd 4: begin oleddcn ⇐ DATA; charreg ⇐ 8'h00; state ⇐ WRITE; stateback ⇐ SCAN; end 灏8鐐归樀缂栫▼88
5'd 5: begin oleddcn ⇐ DATA; charreg ⇐ 8'h00; state ⇐ WRITE; stateback ⇐ SCAN; end 灏8鐐归樀缂栫▼88
5'd 6: begin oleddcn ⇐ DATA; charreg ⇐ 8'h00; state ⇐ WRITE; stateback ⇐ SCAN; end 灏8鐐归樀缂栫▼88
5'd 7: begin oleddcn ⇐ DATA; charreg ⇐ mem[char[(num*8)+:8]][39:32]; state ⇐ WRITE; stateback ⇐ SCAN; end
5'd 8: begin oleddcn ⇐ DATA; charreg ⇐ mem[char[(num*8)+:8]][31:24]; state ⇐ WRITE; stateback ⇐ SCAN; end
5'd 9: begin oleddcn ⇐ DATA; charreg ⇐ mem[char[(num*8)+:8]][23:16]; state ⇐ WRITE; stateback ⇐ SCAN; end
5'd10: begin oleddcn ⇐ DATA; charreg ⇐ mem[char[(num*8)+:8]][15: 8]; state ⇐ WRITE; stateback ⇐ SCAN; end
5'd11: begin oleddcn ⇐ DATA; charreg ⇐ mem[char[(num*8)+:8]][ 7: 0]; state ⇐ WRITE; stateback ⇐ SCAN; end
5'd12: begin state ⇐ MAIN; end
default: state ⇐ IDLE;
endcase
end
lengthhanzi⇐5'd8—–涓€琛屽啓鍏
CHINESE:begin 鏄剧ず姹夊瓧
if(cntchinese == 5'd11) begin
if(lengthhanzi>=5'd2) cntchinese ⇐ 5'd3;
else cntchinese ⇐ cntchinese + 1'b1;
end
else if(cntchinese == 5'd12) cntchinese ⇐ 1'b0;
else cntchinese ⇐ cntchinese+1'b1;
case(cntchinese)
5'd 0: begin oleddcn ⇐ CMD; charreg ⇐ yp; state ⇐ WRITE; stateback ⇐ CHINESE; end 瀹氫綅鍒楅〉鍦板潃
5'd 1: begin oleddcn ⇐ CMD; charreg ⇐ 8'h00; state ⇐ WRITE; stateback ⇐ CHINESE; end 瀹氫綅琛屽湴鍧€浣庝綅
5'd 2: begin oleddcn ⇐ CMD; charreg ⇐ 8'h10; state ⇐ WRITE; stateback ⇐ CHINESE; end 瀹氫綅琛屽湴鍧€楂樹綅
5'd 3: begin lengthhanzi ⇐ lengthhanzi - 1'b1;endlengthhanzi鍒濆=9锛氭瘡琛岄暱搴︿负8
5'd 4: begin oleddcn ⇐ DATA; charreg ⇐ memhanzi[hanzi_fuzhujishu*8+8-length_hanzi][63:56]; state ⇐ WRITE; stateback ⇐ CHINESE; end
5'd 5: begin oleddcn ⇐ DATA; charreg ⇐ memhanzi[hanzi_fuzhujishu*8+8-length_hanzi][55:48]; state ⇐ WRITE; stateback ⇐ CHINESE; end
5'd 6: begin oleddcn ⇐ DATA; charreg ⇐ memhanzi[hanzi_fuzhujishu*8+8-length_hanzi][47:40]; state ⇐ WRITE; stateback ⇐ CHINESE; end
5'd 7: begin oleddcn ⇐ DATA; charreg ⇐ memhanzi[hanzi_fuzhujishu*8+8-length_hanzi][39:32]; state ⇐ WRITE; stateback ⇐ CHINESE; end
5'd 8: begin oleddcn ⇐ DATA; charreg ⇐ memhanzi[hanzi_fuzhujishu*8+8-length_hanzi][31:24]; state ⇐ WRITE; stateback ⇐ CHINESE; end
5'd 9: begin oleddcn ⇐ DATA; charreg ⇐ memhanzi[hanzi_fuzhujishu*8+8-length_hanzi][23:16]; state ⇐ WRITE; stateback ⇐ CHINESE; end
5'd10: begin oleddcn ⇐ DATA; charreg ⇐ memhanzi[hanzi_fuzhujishu*8+8-length_hanzi][15: 8]; state ⇐ WRITE; stateback ⇐ CHINESE; end
5'd11: begin oleddcn ⇐ DATA; charreg ⇐ memhanzi[hanzi_fuzhujishu*8+8-length_hanzi][ 7: 0]; state ⇐ WRITE; stateback ⇐ CHINESE; end
5'd12: begin state ⇐ MAIN; end
default: state ⇐ IDLE;
endcase
end
WRITE:begin WRITE鐘舵€侊紝灏嗘暟鎹寜鐓PI鏃跺簭鍙戦€佺粰灞忓箷
if(cntwrite >= 5'd17) cntwrite ⇐ 1'b0;
else cntwrite ⇐ cntwrite + 1'b1;
case(cntwrite)
5'd 0: begin oledcsn ⇐ LOW; end 9浣嶆暟鎹渶楂樹綅涓哄懡浠ゆ暟鎹帶鍒朵綅
5'd 1: begin oledclk ⇐ LOW; oleddat ⇐ charreg[7]; end 鍏堝彂楂樹綅鏁版嵁
5'd 2: begin oledclk ⇐ HIGH; end
5'd 3: begin oledclk ⇐ LOW; oleddat ⇐ charreg[6]; end
5'd 4: begin oledclk ⇐ HIGH; end
5'd 5: begin oledclk ⇐ LOW; oleddat ⇐ charreg[5]; end
5'd 6: begin oledclk ⇐ HIGH; end
5'd 7: begin oledclk ⇐ LOW; oleddat ⇐ charreg[4]; end
5'd 8: begin oledclk ⇐ HIGH; end
5'd 9: begin oledclk ⇐ LOW; oleddat ⇐ charreg[3]; end
5'd10: begin oledclk ⇐ HIGH; end
5'd11: begin oledclk ⇐ LOW; oleddat ⇐ charreg[2]; end
5'd12: begin oledclk ⇐ HIGH; end
5'd13: begin oledclk ⇐ LOW; oleddat ⇐ charreg[1]; end
5'd14: begin oledclk ⇐ HIGH; end
5'd15: begin oledclk ⇐ LOW; oleddat ⇐ charreg[0]; end 鍚庡彂浣庝綅鏁版嵁
5'd16: begin oledclk ⇐ HIGH; end
5'd17: begin oledcsn ⇐ HIGH; state ⇐ DELAY; end
default: state ⇐ IDLE;
endcase
end
DELAY:begin 寤舵椂鐘舵€
if(cntdelay >= numdelay) begin
cntdelay ⇐ 16'd0; state ⇐ stateback;
end else cntdelay ⇐ cntdelay + 1'b1;
end
default:state ⇐ IDLE;
endcase
end
end
OLED閰嶇疆鎸囦护鏁版嵁
always@(posedge rstn)
begin
cmd[0 ] = {8'hae};
cmd[1 ] = {8'hd5};
cmd[2 ] = {8'h80};
cmd[3 ] = {8'ha8};
cmd[4 ] = {8'h3f};
cmd[5 ] = {8'hd3};
cmd[6 ] = {8'h00};
cmd[7 ] = {8'h40};
cmd[8 ] = {8'h8d};
cmd[9 ] = {8'h14};
cmd[10] = {8'h20};
cmd[11] = {8'h02};
cmd[12] = {8'hc8};
cmd[13] = {8'ha1};
cmd[14] = {8'hda};
cmd[15] = {8'h12};
cmd[16] = {8'h81};
cmd[17] = {8'hcf};
cmd[18] = {8'hd9};
cmd[19] = {8'hf1};
cmd[20] = {8'hdb};
cmd[21] = {8'h40};
cmd[22] = {8'haf};
end
5*8鐐归樀瀛楀簱鏁版嵁
always@(posedge rstn)
begin
mem[ 0] = {8'h3E, 8'h51, 8'h49, 8'h45, 8'h3E}; 48 0
mem[ 1] = {8'h00, 8'h42, 8'h7F, 8'h40, 8'h00}; 49 1
mem[ 2] = {8'h42, 8'h61, 8'h51, 8'h49, 8'h46}; 50 2
mem[ 3] = {8'h21, 8'h41, 8'h45, 8'h4B, 8'h31}; 51 3
mem[ 4] = {8'h18, 8'h14, 8'h12, 8'h7F, 8'h10}; 52 4
mem[ 5] = {8'h27, 8'h45, 8'h45, 8'h45, 8'h39}; 53 5
mem[ 6] = {8'h3C, 8'h4A, 8'h49, 8'h49, 8'h30}; 54 6
mem[ 7] = {8'h01, 8'h71, 8'h09, 8'h05, 8'h03}; 55 7
mem[ 8] = {8'h36, 8'h49, 8'h49, 8'h49, 8'h36}; 56 8
mem[ 9] = {8'h06, 8'h49, 8'h49, 8'h29, 8'h1E}; 57 9
mem[ 10] = {8'h7C, 8'h12, 8'h11, 8'h12, 8'h7C}; 65 A
mem[ 11] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h36}; 66 B
mem[ 12] = {8'h3E, 8'h41, 8'h41, 8'h41, 8'h22}; 67 C
mem[ 13] = {8'h7F, 8'h41, 8'h41, 8'h22, 8'h1C}; 68 D
mem[ 14] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h41}; 69 E
mem[ 15] = {8'h7F, 8'h09, 8'h09, 8'h09, 8'h01}; 70 F
mem[ 32] = {8'h00, 8'h00, 8'h00, 8'h00, 8'h00}; 32 sp
mem[ 33] = {8'h00, 8'h00, 8'h2f, 8'h00, 8'h00}; 33 !
mem[ 34] = {8'h00, 8'h07, 8'h00, 8'h07, 8'h00}; 34
mem[ 35] = {8'h14, 8'h7f, 8'h14, 8'h7f, 8'h14}; 35 #
mem[ 36] = {8'h24, 8'h2a, 8'h7f, 8'h2a, 8'h12}; 36 $
mem[ 37] = {8'h62, 8'h64, 8'h08, 8'h13, 8'h23}; 37 %
mem[ 38] = {8'h36, 8'h49, 8'h55, 8'h22, 8'h50}; 38 &
mem[ 39] = {8'h00, 8'h05, 8'h03, 8'h00, 8'h00}; 39 '
mem[ 40] = {8'h00, 8'h1c, 8'h22, 8'h41, 8'h00}; 40 (
mem[ 41] = {8'h00, 8'h41, 8'h22, 8'h1c, 8'h00}; 41 )
mem[ 42] = {8'h14, 8'h08, 8'h3E, 8'h08, 8'h14}; 42
mem[ 43] = {8'h08, 8'h08, 8'h3E, 8'h08, 8'h08}; 43 +
mem[ 44] = {8'h00, 8'h00, 8'hA0, 8'h60, 8'h00}; 44 ,
mem[ 45] = {8'h08, 8'h08, 8'h08, 8'h08, 8'h08}; 45 -
mem[ 46] = {8'h00, 8'h60, 8'h60, 8'h00, 8'h00}; 46 .
mem[ 47] = {8'h20, 8'h10, 8'h08, 8'h04, 8'h02}; 47 /
mem[ 48] = {8'h3E, 8'h51, 8'h49, 8'h45, 8'h3E}; 48 0
mem[ 49] = {8'h00, 8'h42, 8'h7F, 8'h40, 8'h00}; 49 1
mem[ 50] = {8'h42, 8'h61, 8'h51, 8'h49, 8'h46}; 50 2
mem[ 51] = {8'h21, 8'h41, 8'h45, 8'h4B, 8'h31}; 51 3
mem[ 52] = {8'h18, 8'h14, 8'h12, 8'h7F, 8'h10}; 52 4
mem[ 53] = {8'h27, 8'h45, 8'h45, 8'h45, 8'h39}; 53 5
mem[ 54] = {8'h3C, 8'h4A, 8'h49, 8'h49, 8'h30}; 54 6
mem[ 55] = {8'h01, 8'h71, 8'h09, 8'h05, 8'h03}; 55 7
mem[ 56] = {8'h36, 8'h49, 8'h49, 8'h49, 8'h36}; 56 8
mem[ 57] = {8'h06, 8'h49, 8'h49, 8'h29, 8'h1E}; 57 9
mem[ 58] = {8'h00, 8'h36, 8'h36, 8'h00, 8'h00}; 58 :
mem[ 59] = {8'h00, 8'h56, 8'h36, 8'h00, 8'h00}; 59 ;
mem[ 60] = {8'h08, 8'h14, 8'h22, 8'h41, 8'h00}; 60 <
mem[ 61] = {8'h14, 8'h14, 8'h14, 8'h14, 8'h14}; 61 =
mem[ 62] = {8'h00, 8'h41, 8'h22, 8'h14, 8'h08}; 62 >
mem[ 63] = {8'h02, 8'h01, 8'h51, 8'h09, 8'h06}; 63 ?
mem[ 64] = {8'h32, 8'h49, 8'h59, 8'h51, 8'h3E}; 64 @
mem[ 65] = {8'h7C, 8'h12, 8'h11, 8'h12, 8'h7C}; 65 A
mem[ 66] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h36}; 66 B
mem[ 67] = {8'h3E, 8'h41, 8'h41, 8'h41, 8'h22}; 67 C
mem[ 68] = {8'h7F, 8'h41, 8'h41, 8'h22, 8'h1C}; 68 D
mem[ 69] = {8'h7F, 8'h49, 8'h49, 8'h49, 8'h41}; 69 E
mem[ 70] = {8'h7F, 8'h09, 8'h09, 8'h09, 8'h01}; 70 F
mem[ 71] = {8'h3E, 8'h41, 8'h49, 8'h49, 8'h7A}; 71 G
mem[ 72] = {8'h7F, 8'h08, 8'h08, 8'h08, 8'h7F}; 72 H
mem[ 73] = {8'h00, 8'h41, 8'h7F, 8'h41, 8'h00}; 73 I
mem[ 74] = {8'h20, 8'h40, 8'h41, 8'h3F, 8'h01}; 74 J
mem[ 75] = {8'h7F, 8'h08, 8'h14, 8'h22, 8'h41}; 75 K
mem[ 76] = {8'h7F, 8'h40, 8'h40, 8'h40, 8'h40}; 76 L
mem[ 77] = {8'h7F, 8'h02, 8'h0C, 8'h02, 8'h7F}; 77 M
mem[ 78] = {8'h7F, 8'h04, 8'h08, 8'h10, 8'h7F}; 78 N
mem[ 79] = {8'h3E, 8'h41, 8'h41, 8'h41, 8'h3E}; 79 O
mem[ 80] = {8'h7F, 8'h09, 8'h09, 8'h09, 8'h06}; 80 P
mem[ 81] = {8'h3E, 8'h41, 8'h51, 8'h21, 8'h5E}; 81 Q
mem[ 82] = {8'h7F, 8'h09, 8'h19, 8'h29, 8'h46}; 82 R
mem[ 83] = {8'h46, 8'h49, 8'h49, 8'h49, 8'h31}; 83 S
mem[ 84] = {8'h01, 8'h01, 8'h7F, 8'h01, 8'h01}; 84 T
mem[ 85] = {8'h3F, 8'h40, 8'h40, 8'h40, 8'h3F}; 85 U
mem[ 86] = {8'h1F, 8'h20, 8'h40, 8'h20, 8'h1F}; 86 V
mem[ 87] = {8'h3F, 8'h40, 8'h38, 8'h40, 8'h3F}; 87 W
mem[ 88] = {8'h63, 8'h14, 8'h08, 8'h14, 8'h63}; 88 X
mem[ 89] = {8'h07, 8'h08, 8'h70, 8'h08, 8'h07}; 89 Y
mem[ 90] = {8'h61, 8'h51, 8'h49, 8'h45, 8'h43}; 90 Z
mem[ 91] = {8'h00, 8'h7F, 8'h41, 8'h41, 8'h00}; 91 [
mem[ 92] = {8'h55, 8'h2A, 8'h55, 8'h2A, 8'h55}; 92 .
mem[ 93] = {8'h00, 8'h41, 8'h41, 8'h7F, 8'h00}; 93 ]
mem[ 94] = {8'h04, 8'h02, 8'h01, 8'h02, 8'h04}; 94 ^
mem[ 95] = {8'h40, 8'h40, 8'h40, 8'h40, 8'h40}; 95
mem[ 96] = {8'h00, 8'h01, 8'h02, 8'h04, 8'h00}; 96 '
mem[ 97] = {8'h20, 8'h54, 8'h54, 8'h54, 8'h78}; 97 a
mem[ 98] = {8'h7F, 8'h48, 8'h44, 8'h44, 8'h38}; 98 b
mem[ 99] = {8'h38, 8'h44, 8'h44, 8'h44, 8'h20}; 99 c
mem[100] = {8'h38, 8'h44, 8'h44, 8'h48, 8'h7F}; 100 d
mem[101] = {8'h38, 8'h54, 8'h54, 8'h54, 8'h18}; 101 e
mem[102] = {8'h08, 8'h7E, 8'h09, 8'h01, 8'h02}; 102 f
mem[103] = {8'h18, 8'hA4, 8'hA4, 8'hA4, 8'h7C}; 103 g
mem[104] = {8'h7F, 8'h08, 8'h04, 8'h04, 8'h78}; 104 h
mem[105] = {8'h00, 8'h44, 8'h7D, 8'h40, 8'h00}; 105 i
mem[106] = {8'h40, 8'h80, 8'h84, 8'h7D, 8'h00}; 106 j
mem[107] = {8'h7F, 8'h10, 8'h28, 8'h44, 8'h00}; 107 k
mem[108] = {8'h00, 8'h41, 8'h7F, 8'h40, 8'h00}; 108 l
mem[109] = {8'h7C, 8'h04, 8'h18, 8'h04, 8'h78}; 109 m
mem[110] = {8'h7C, 8'h08, 8'h04, 8'h04, 8'h78}; 110 n
mem[111] = {8'h38, 8'h44, 8'h44, 8'h44, 8'h38}; 111 o
mem[112] = {8'hFC, 8'h24, 8'h24, 8'h24, 8'h18}; 112 p
mem[113] = {8'h18, 8'h24, 8'h24, 8'h18, 8'hFC}; 113 q
mem[114] = {8'h7C, 8'h08, 8'h04, 8'h04, 8'h08}; 114 r
mem[115] = {8'h48, 8'h54, 8'h54, 8'h54, 8'h20}; 115 s
mem[116] = {8'h04, 8'h3F, 8'h44, 8'h40, 8'h20}; 116 t
mem[117] = {8'h3C, 8'h40, 8'h40, 8'h20, 8'h7C}; 117 u
mem[118] = {8'h1C, 8'h20, 8'h40, 8'h20, 8'h1C}; 118 v
mem[119] = {8'h3C, 8'h40, 8'h30, 8'h40, 8'h3C}; 119 w
mem[120] = {8'h44, 8'h28, 8'h10, 8'h28, 8'h44}; 120 x
mem[121] = {8'h1C, 8'hA0, 8'hA0, 8'hA0, 8'h7C}; 121 y
mem[122] = {8'h44, 8'h64, 8'h54, 8'h4C, 8'h44}; 122 z
end
姹夊瓧锛氱‖绂惧鍫
always@(posedge rstn)
begin
memhanzi[ 0] = {8'h04,8'h84,8'hE4,8'h5C,8'h44,8'hC4,8'h00,8'hF2}; 48 0
memhanzi[ 1] = {8'h92,8'h92,8'hFE,8'h92,8'h92,8'hF2,8'h02,8'h00}; 49 1
memhanzi[ 8] = {8'h02,8'h01,8'h7F,8'h10,8'h10,8'h3F,8'h80,8'h8F}; 50 2
memhanzi[ 9] = {8'h54,8'h24,8'h5F,8'h44,8'h84,8'h87,8'h80,8'h00}; 51 3
memhanzi[ 2] = {8'h00,8'h40,8'h44,8'h44,8'h44,8'h44,8'hC4,8'hFC}; 52 4
memhanzi[ 3] = {8'hC2,8'h42,8'h42,8'h43,8'h42,8'h40,8'h00,8'h00}; 53 5
memhanzi[ 10] = {8'h20,8'h20,8'h10,8'h08,8'h04,8'h03,8'h00,8'hFF}; 54 6
memhanzi[ 11] = {8'h00,8'h03,8'h04,8'h08,8'h10,8'h20,8'h20,8'h00}; 55 7
memhanzi[ 4] = {8'h40,8'h30,8'h11,8'h96,8'h90,8'h90,8'h91,8'h96}; 56 8
memhanzi[ 5 ] = {8'h90,8'h90,8'h98,8'h14,8'h13,8'h50,8'h30,8'h00}; 48 0
memhanzi[ 12] = {8'h04,8'h04,8'h04,8'h04,8'h04,8'h44,8'h84,8'h7E}; 49 1
memhanzi[ 13] = {8'h06,8'h05,8'h04,8'h04,8'h04,8'h04,8'h04,8'h00}; 50 2
memhanzi[ 6] = {8'h20,8'h18,8'h08,8'hEA,8'h2C,8'h28,8'h28,8'h2F}; 51 3
memhanzi[ 7] = {8'h28,8'h28,8'h2C,8'hEA,8'h08,8'h28,8'h18,8'h00}; 52 4
memhanzi[ 14] = {8'h40,8'h40,8'h48,8'h49,8'h49,8'h49,8'h49,8'h7F}; 53 5
memhanzi[ 15] = {8'h49,8'h49,8'h49,8'h49,8'h48,8'h40,8'h40,8'h00}; 54 6
memhanzi[ 16] ={8'h40,8'h30,8'hEF,8'h24,8'h24,8'h00,8'hFE,8'h92};閿娇娉2 3
memhanzi[ 17] ={8'h92,8'h92,8'hF2,8'h92,8'h92,8'h9E,8'h80,8'h00};
memhanzi[ 18] ={8'h40,8'h40,8'h40,8'h7C,8'h40,8'h40,8'h40,8'h7F};
memhanzi[ 19] ={8'h44,8'h44,8'h44,8'h44,8'h44,8'h40,8'h40,8'h00};
memhanzi[ 20] ={8'h10,8'h60,8'h02,8'h0C,8'hC0,8'h00,8'hF8,8'h88};
memhanzi[ 21] ={8'h88,8'h88,8'hFF,8'h88,8'h88,8'hA8,8'h18,8'h00};
memhanzi[ 22] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 23] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 24] ={8'h01,8'h01,8'h7F,8'h21,8'h91,8'h60,8'h1F,8'h00};
memhanzi[ 25] ={8'hFC,8'h44,8'h47,8'h44,8'h44,8'hFC,8'h00,8'h00};
memhanzi[ 26] ={8'h00,8'h00,8'h7F,8'h40,8'h50,8'h48,8'h44,8'h43};
memhanzi[ 27] ={8'h44,8'h48,8'h50,8'h40,8'hFF,8'h00,8'h00,8'h00};
memhanzi[ 28] ={8'h04,8'h04,8'h7C,8'h03,8'h80,8'h60,8'h1F,8'h80};
memhanzi[ 29] ={8'h43,8'h2C,8'h10,8'h28,8'h46,8'h81,8'h80,8'h00};/“娉,2/
memhanzi[ 30] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 31] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 32] ={8'h00,8'h04,8'h84,8'h84,8'h84,8'h84,8'h84,8'h84}; 涓夎娉5
memhanzi[ 33] = {8'h84,8'h84,8'h84,8'h84,8'h84,8'h04,8'h00,8'h00};
memhanzi[ 34] ={8'h20,8'h10,8'hE8,8'h24,8'h27,8'h24,8'h24,8'hE4};
memhanzi[ 35] ={8'h24,8'h34,8'h2C,8'h20,8'hE0,8'h00,8'h00,8'h00};
memhanzi[ 36] ={8'h10,8'h60,8'h02,8'h0C,8'hC0,8'h00,8'hF8,8'h88};
memhanzi[ 37] ={8'h88,8'h88,8'hFF,8'h88,8'h88,8'hA8,8'h18,8'h00};
memhanzi[ 38] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 39] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 40] ={8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20};
memhanzi[ 41] ={8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h20,8'h00};
memhanzi[ 42] ={8'h80,8'h60,8'h1F,8'h09,8'h09,8'h09,8'h09,8'h7F};
memhanzi[ 43] ={8'h09,8'h09,8'h49,8'h89,8'h7F,8'h00,8'h00,8'h00};/“瑙,4/
memhanzi[ 44] ={8'h04,8'h04,8'h7C,8'h03,8'h80,8'h60,8'h1F,8'h80};
memhanzi[ 45] ={8'h43,8'h2C,8'h10,8'h28,8'h46,8'h81,8'h80,8'h00};/“娉,5/
memhanzi[ 46] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 47] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 48] ={8'h08,8'h08,8'h08,8'h08,8'h08,8'hF8,8'h89,8'h8E};
memhanzi[ 49] ={8'h88,8'h88,8'h88,8'h88,8'h08,8'h08,8'h08,8'h00};
memhanzi[ 50] ={8'h10,8'h60,8'h02,8'h0C,8'hC0,8'h00,8'hF8,8'h88};
memhanzi[ 51] ={8'h88,8'h88,8'hFF,8'h88,8'h88,8'hA8,8'h18,8'h00};
memhanzi[ 52] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 53] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 54] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 55] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 56] ={8'h00,8'h80,8'h40,8'h20,8'h18,8'h07,8'h00,8'h00};
memhanzi[ 57] ={8'h40,8'h80,8'h40,8'h3F,8'h00,8'h00,8'h00,8'h00};/“鏂,6/
memhanzi[ 58] ={8'h04,8'h04,8'h7C,8'h03,8'h80,8'h60,8'h1F,8'h80};
memhanzi[ 59] = {8'h43,8'h2C,8'h10,8'h28,8'h46,8'h81,8'h80,8'h00};/“娉,7/
memhanzi[ 60] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 61] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 62] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 63] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 64] ={8'h00,8'h02,8'h02,8'hC2,8'h02,8'h02,8'h02,8'hFE};姝ｅ鸡娉89
memhanzi[ 65] ={8'h82,8'h82,8'h82,8'h82,8'h82,8'h02,8'h00,8'h00};
memhanzi[ 66] ={8'h02,8'hE2,8'h22,8'h22,8'h3E,8'h00,8'h08,8'h88};
memhanzi[ 67] = {8'h48,8'h39,8'h0E,8'h08,8'hC8,8'h08,8'h08,8'h00};
memhanzi[ 68] ={8'h10,8'h60,8'h02,8'h0C,8'hC0,8'h00,8'hF8,8'h88};
memhanzi[ 69] ={8'h88,8'h88,8'hFF,8'h88,8'h88,8'hA8,8'h18,8'h00};
memhanzi[ 70] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 71] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
memhanzi[ 72] ={8'h40,8'h40,8'h40,8'h7F,8'h40,8'h40,8'h40,8'h7F};
memhanzi[ 73] ={8'h40,8'h40,8'h40,8'h40,8'h40,8'h40,8'h40,8'h00};/“姝,8/
memhanzi[ 74] ={8'h00,8'h43,8'h82,8'h42,8'h3E,8'h00,8'h21,8'h71};
memhanzi[ 75] ={8'h29,8'h25,8'h23,8'h21,8'h28,8'h70,8'h00,8'h00};/“寮,9/
memhanzi[ 76] ={8'h04,8'h04,8'h7C,8'h03,8'h80,8'h60,8'h1F,8'h80};
memhanzi[ 77] ={8'h43,8'h2C,8'h10,8'h28,8'h46,8'h81,8'h80,8'h00};/“娉,10/
memhanzi[ 78] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
mem_hanzi[ 79] ={8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00};
end
endmodule
</code>