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| - | <!-- ************************************** | + | # step |
| - | ** FEATURES & SPECIFICIATIONS ** | + | |
| - | ************************************** --> | + | |
| - | + | ||
| - | <h2 id="Features">Features & Specifications</h2> | + | |
| - | <img style="float: right; padding-left: 0.5em; width: 45%" alt="(ESP32 Function Block Diagram)" src="./images/_resources/ESP32_Function_Block_Diagram.svg"> | + | |
| - | <p>See the <i><a href="https://espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf">ESP32 Datasheet</a></i> | + | |
| - | for information on ESP32 chips and the | + | |
| - | <i><a href="https://espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf">ESP32-PICO-D4 Datasheet</a></i> | + | |
| - | for information on the SiP module. | + | |
| - | </p> | + | |
| - | <ul> | + | |
| - | <li><b>Processors:</b> | + | |
| - | <ul> | + | |
| - | <li><b>Main processor:</b> Tensilica Xtensa 32-bit LX6 microprocessor | + | |
| - | <ul> | + | |
| - | <li><b>Cores:</b> 2 or 1 (depending on variation) | + | |
| - | <div class="NoteLesser">All chips in the ESP32 series are dual-core | + | |
| - | except for ESP32-S0WD, which is single-core. | + | |
| - | </div> | + | |
| - | </li> | + | |
| - | <li><b>Clock frequency:</b> up to 240 MHz</li> | + | |
| - | <li><b>Performance:</b> up to 600 <abbr title="Dhrystone MIPS">DMIPS</abbr></li> | + | |
| - | </ul> | + | |
| - | </li> | + | |
| - | <li><b><a href="http://esp-idf.readthedocs.io/en/latest/api-guides/ulp.html">Ultra low power co-processor:</a></b> | + | |
| - | allows you to do ADC conversions, computation, and level | + | |
| - | thresholds while in deep sleep. | + | |
| - | </li> | + | |
| - | </ul> | + | |
| - | </li> | + | |
| - | <li><b>Wireless connectivity:</b> | + | |
| - | <ul> | + | |
| - | <li><b>Wi-Fi:</b> 802.11 b/g/n<span style="color: gray">/e/i</span> (802.11n @ 2.4 GHz up to 150 Mbit/s) | + | |
| - | <!-- | + | |
| - | 150.0 <abbr title="megabits per second">Mbit/s</abbr> data rate @ 802.11n HT40, (40 MHz channel width, 400 ns guard interval, 1 spatial stream, 64-QAM, 5/6 coding rate) | + | |
| - | 72 <abbr title="megabits per second">Mbit/s</abbr> @ 802.11n HT20, | + | |
| - | 54 <abbr title="megabits per second">Mbit/s</abbr> @ 802.11g, | + | |
| - | 11 <abbr title="megabits per second">Mbit/s</abbr> @ 802.11b | + | |
| - | --> | + | |
| - | </li> | + | |
| - | <li><b>Bluetooth:</b> v4.2 BR/EDR and Bluetooth Low Energy (BLE)</li> | + | |
| - | </ul> | + | |
| - | </li> | + | |
| - | <li><b>Memory:</b> | + | |
| - | <ul> | + | |
| - | <li><b>Internal memory:</b> | + | |
| - | <ul> | + | |
| - | <li><b>ROM:</b> 448 <abbr title="kibibyte">KiB</abbr> | + | |
| - | <div class="NoteLesser">For booting and core functions.</div> | + | |
| - | </li> | + | |
| - | <li><b>SRAM:</b> 520 <abbr title="kibibyte">KiB</abbr> | + | |
| - | <div class="NoteLesser">For data and instruction.</div> | + | |
| - | </li> | + | |
| - | <li><b>RTC fast SRAM:</b> 8 <abbr title="kibibyte">KiB</abbr> | + | |
| - | <div class="NoteLesser">For data storage and main CPU during RTC Boot from the deep-sleep mode.</div> | + | |
| - | </li> | + | |
| - | <li><b>RTC slow SRAM:</b> 8 <abbr title="kibibyte">KiB</abbr> | + | |
| - | <div class="NoteLesser">For co-processor accessing during deep-sleep mode.</div> | + | |
| - | </li> | + | |
| - | <li><b>eFuse:</b> 1 <abbr title="kibibit">Kibit</abbr> | + | |
| - | <div class="NoteLesser">Of which 256 bits are used for the system | + | |
| - | (MAC address and chip configuration) and the remaining | + | |
| - | 768 bits are reserved for customer applications, including | + | |
| - | Flash-Encryption and Chip-ID. | + | |
| - | </div> | + | |
| - | </li> | + | |
| - | <li><b>Embedded flash:</b> | + | |
| - | <div class="NoteLesser">Flash connected internally via IO16, IO17, SD_CMD, SD_CLK, SD_DATA_0 and SD_DATA_1 on ESP32-D2WD and ESP32-PICO-D4.</div> | + | |
| - | <ul> | + | |
| - | <li> 0 MiB (ESP32-D0WDQ6, ESP32-D0WD, and ESP32-S0WD chips)</li> | + | |
| - | <li> 2 MiB (ESP32-D2WD chip)</li> | + | |
| - | <li> 4 MiB (ESP32-PICO-D4 SiP module)</li> | + | |
| - | </ul> | + | |
| - | </li> | + | |
| - | </ul> | + | |
| - | </li> | + | |
| - | <li><b>External flash & SRAM:</b> | + | |
| - | ESP32 supports up to four 16 MiB external QSPI flashes and | + | |
| - | SRAMs with hardware encryption based on AES to protect | + | |
| - | developers' programs and data. ESP32 can access the | + | |
| - | external QSPI flash and SRAM through high-speed caches. | + | |
| - | <ul> | + | |
| - | <li>Up to 16 MiB of external flash are memory-mapped | + | |
| - | onto the CPU code space, supporting 8-bit, 16-bit and | + | |
| - | 32-bit access. Code execution is supported. | + | |
| - | </li> | + | |
| - | <li>Up to 8 MiB of external flash/SRAM memory are mapped | + | |
| - | onto the CPU data space, supporting 8-bit, 16-bit | + | |
| - | and 32-bit access. Data-read is supported on the | + | |
| - | flash and SRAM. Data-write is supported on the SRAM. | + | |
| - | </li> | + | |
| - | </ul> | + | |
| - | <div class="NoteLesser">ESP32 chips with embedded flash do not support the | + | |
| - | address mapping between external flash and peripherals. | + | |
| - | </div> | + | |
| - | </li> | + | |
| - | </ul> | + | |
| - | </li> | + | |
| - | <li><b>Peripheral input/output:</b> Rich peripheral interface with DMA | + | |
| - | that includes capacitive touch, ADCs (analog-to-digital converter), | + | |
| - | DACs (digital-to-analog converter), I²C (Inter-Integrated Circuit), | + | |
| - | UART (universal asynchronous receiver/transmitter), | + | |
| - | CAN 2.0 (Controller Area Network), SPI (Serial Peripheral Interface), | + | |
| - | I²S (Integrated Inter-IC Sound), RMII (Reduced Media-Independent | + | |
| - | Interface), PWM (pulse width modulation), and more. | + | |
| - | </li> | + | |
| - | <li><b>Security:</b> | + | |
| - | <ul> | + | |
| - | <li>IEEE 802.11 standard security features all supported, including WFA, WPA/WPA2 and WAPI</li> | + | |
| - | <li>Secure boot</li> | + | |
| - | <li>Flash encryption</li> | + | |
| - | <li>1024-bit OTP, up to 768-bit for customers</li> | + | |
| - | <li>Cryptographic hardware acceleration: AES, SHA-2, RSA, elliptic | + | |
| - | curve cryptography (ECC), random number generator (RNG) | + | |
| - | </li> | + | |
| - | </ul> | + | |
| - | </li> | + | |
| - | </ul> | + | |
| - | + | ||
| - | <div class="NoteLesser"> | + | |
| - | Clarification note: In this context, "RTC" is a bit of an "Espressifism" | + | |
| - | because it's used as shorthand for the low-power and analog subsystem which | + | |
| - | is separate from the CPU and the main "digital" peripherals ("digital" is | + | |
| - | another Espressifism). There is some real time clock functionality as part | + | |
| - | of the RTC subsystem, but there's also a lot of other stuff. | + | |
| - | <!-- Source: ProjectGus. | + | |
| - | #ESP32 Channel, Freenode Internet Relay Chat Network <irc://irc.freenode.net/#ESP32>. | + | |
| - | 2017 May 8, 5:54 AM UTC. | + | |
| - | --> | + | |
| - | <!-- ULP can access most of the "RTC" peripherals, and certainly the ADC | + | |
| - | (which is most of the hall effect functionality) so I believe it can | + | |
| - | access the hall effect sensor. | + | |
| - | --> | + | |
| - | </div> | + | |
| - | + | ||
| - | </html> | + | |