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analog_discovery_2_参考手册 [2016/05/31 14:07] admin [2.3. Scope Reference and Offset] |
analog_discovery_2_参考手册 [2016/08/08 23:57] gongyu [6. Power Supplies and Control] |
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| - | ==== 2.6.1. Analog Section ==== | + | ==== 2.6.1. 模拟部分 ==== |
| - | The Analog Discovery 2 uses a dual channel, high speed, low power, 14-bit, 105MSPS ADC (Analog part number [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9648/products/product.html|AD9648]]), as shown in [[analog_discovery_2:refmanual#figure_9|Fig. 9]] . | + | Analog Discovery 2 采用了双通道、高速、14位、105Msps ADC（型号为[[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9648/products/product.html|AD9648]]), 如图[[analog_discovery_2:refmanual#figure_9|图9]] . |
| - | {{ :analog_discovery_figure_9.png |Figure 9. ADC - analog section.}} | + | {{ :analog_discovery_figure_9.png |图9. ADC-模拟部分.}} |
| //{{anchor:figure_9:Figure 9. ADC - analog section.}}// | //{{anchor:figure_9:Figure 9. ADC - analog section.}}// | ||
| - | The important features of AD9648: | + | AD9648的主要性能: |
| * SNR = 74.5dBFS @70 MHz | * SNR = 74.5dBFS @70 MHz | ||
| * SFDR =91dBc @70 MHz | * SFDR =91dBc @70 MHz | ||
| - | * Low power: 78mW/channel ADC core@ 125MSPS | + | * 低功耗: 78mW/ADC通道 @ 125MSPS |
| - | * Differential analog input with 650 MHz bandwidth | + | * 650MHz差分模拟输入带宽 |
| - | * IF sampling frequencies to 200 MHz | + | * 中频取样频率到200MHz |
| - | * On-chip voltage reference and sample-and-hold circuit | + | * 片上电压基准和取样保持电路 |
| - | * 2 V p-p differential analog input | + | * 2Vp-p差分模拟输入 |
| * DNL = ±0.35 LSB | * DNL = ±0.35 LSB | ||
| - | * Serial port control options | + | * 可选串行端口控制 |
| - | * Offset binary, gray code, or two's complement data format | + | * 偏移二进制, gray码, 或2的补码数据格式 |
| - | * Optional clock duty cycle stabilizer | + | * 可选的时钟占空比稳定器 |
| - | * Integer 1-to-8 input clock divider | + | * 输入时钟可以整数（1到8）分频 |
| - | * Data output multiplex option | + | * 可选数据输出复用 |
| - | * Built-in selectable digital test pattern generation | + | * 内建可选的数字测试模式发生器 |
| - | * Energy-saving power-down modes | + | * 节能断电模式 |
| - | * Data clock out with programmable clock and data alignment | + | * 可以编程的时钟／数据对齐的数据时钟输出 |
| The differential inputs are driven via a low-pass filter comprised of C141 together with R10 through R13, in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by two for operating at a constant 100 MHz sampling rate. An external reference voltage is used, buffered by IC 19. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage. | The differential inputs are driven via a low-pass filter comprised of C141 together with R10 through R13, in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by two for operating at a constant 100 MHz sampling rate. An external reference voltage is used, buffered by IC 19. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage. | ||
| - | The differential input voltage range is: | + | 差分输入电压范围: |
| $$-1V<V_{ADC\;diff}<1V\label{19}\tag{19}$$ | $$-1V<V_{ADC\;diff}<1V\label{19}\tag{19}$$ | ||
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| ---- | ---- | ||
| - | ====== 6. Power Supplies and Control ====== | + | ====== 6. 电源和控制 ====== |
| - | + | 此部分为所有的电源监测和控制电路，内部的电源以及用户电源。 | |
| - | This block includes all power monitoring and control circuitry, internal power supplies, and user power supplies. | + | |