3.3.3 Verilog HDL建模描述

（1）顶层文件step.v。
// **************************************************************
// File name	:  step
// Module name	:  step
//
// Author		:  STEP 
// Date			:  2023/3/31 
// Version		:  V 1.0 
// Description	:  顶层模块。
// 
// Modification history
//--------------------------------------------------------------------------
// $Log$
//
// *********************************************************************

module step
(
	input				rst_n,			// system reset, active low
	inout         		one_wire,
	output				fpga_tx	//UART发送输出	
);

HSOSC #(
.CLKHF_DIV ("0b10") 
) OSCInst0 ( 
.CLKHFEN (1'b1   ), 
.CLKHFPU (1'b1   ), 
.CLKHF   (clk)
);

wire	[15:0]	data_out;
//Drive DS18B20Z to get temperature code
DS18B20Z DS18B20Z_uut
(
.clk					(clk			),	// system clock
.rst_n					(rst_n			),	// system reset, active low
.one_wire				(one_wire		),	// ds18b20z one-wire-bus
.data_out				(data_out		)	// ds18b20z data_out
);

// judge sign of temperature
wire temperature_flag = data_out[15:11]? 1'b0:1'b1;
// complement if negative
wire [10:0] temperature_code = temperature_flag? data_out[10:0]:(~data_out[10:0])+1'b1; 
// translate temperature_code to real temperature
wire [20:0] bin_code = temperature_code * 16'd625;
wire [24:0] bcd_code; //十位[23:20],个位[19:16],小数位[14:12]
//Translate binary code to bcd code
bin_to_bcd bin_to_bcd_uut
(
.rst_n					(rst_n			),	// system reset, active low
.bin_code				(bin_code		),	// binary code
.bcd_code				(bcd_code		)	// bcd code
);

wire rx_data_valid;
wire [7:0]	rx_data;
wire tx_data_valid;
wire [7:0]	tx_data;
//Uart_Bus module
Uart_Bus u1
(	
.clk					(clk			),	//系统时钟 12MHz
.rst_n					(rst_n			),	//系统复位，低有效
//负责FPGA接收UART芯片的数据
.uart_rx				(fpga_rx		),	//UART接收输入
.rx_data_valid			(rx_data_valid	),	//接收数据有效脉冲
.rx_data_out			(rx_data		),	//接收到的数据     8位
//负责FPGA发送数据给UART芯片
.tx_data_valid			(tx_data_valid	),
.tx_data_in				(tx_data		),
.uart_tx				(fpga_tx		)
);



control control_s
(
.clk					(clk			),	// system clock
.rst_n					(rst_n			),	// system reset, active low
.temp_in				(bcd_code[23:12]		),	// ds18b20z data_out
.rx_data_valid        	(rx_data_valid	),
.rx_data_in  			(rx_data	 	),
.tx_data_valid        	(tx_data_valid	),
.tx_data_out  			(tx_data	 	)

);

endmodule

（2）center_control.v。

// **************************************************************
// File name	:  center_control
// Module name	:  control
//
// Author		:  STEP 
// Date			:  2023/3/31 
// Version		:  V 1.0 
// Description	:  将BCD码转换为ASCII码。
// 
// Modification history
//--------------------------------------------------------------------------
// $Log$
//
// *********************************************************************

module control
(
	input				clk,			// system clock
	input				rst_n,			// system reset, active low
	input       [11:0] temp_in,
	input              	rx_data_valid,
	input       [7:0]  rx_data_in,
	
	output  reg 		tx_data_valid,
	output  reg [7:0]	tx_data_out,		
	output	reg		[15:0]	cycle
); 

reg temp_tx_flag;

	

	
	always @(posedge clk or negedge rst_n)begin     
		if(!rst_n) 
			temp_tx_flag<=1'b0;
		else
			temp_tx_flag<=1'b1;
	end
	
	
	reg [23:0] cnt_uart;
	always @(posedge clk or negedge rst_n)begin //计时一秒
		if(!rst_n) cnt_uart <= 1'b0;
		else if(cnt_uart >= 24'd11_999_999) cnt_uart <= 1'b0;
		else if (temp_tx_flag) cnt_uart <= cnt_uart + 1'b1;
		else cnt_uart <= cnt_uart;
	end
	
	
	
	always @(posedge clk or negedge rst_n)begin      //*********************每秒发一个温度时间数据，字符串显示***********************//
	if(!rst_n) begin 
		tx_data_valid <= 1'b0; 
		tx_data_out <= 1'b0; 
	end else begin
		if(temp_tx_flag)begin       //发送温度数据
			if(cnt_uart == 24'd9_099_999 ) begin //温度高位
				tx_data_valid <= 1'b1; 
				tx_data_out <= {4'd3,temp_in[11:8]};
			end 
			else if(cnt_uart == 24'd9_599_999 ) begin //温度低位
				tx_data_valid <= 1'b1; 
				tx_data_out <= {4'd3,temp_in[7:4]};
			end 
			else if(cnt_uart == 24'd10_099_999 ) begin //“.”
				tx_data_valid <= 1'b1; 
				tx_data_out <= 8'd46;
			end
			else if(cnt_uart == 24'd10_599_999 ) begin //温度.高位
				tx_data_valid <= 1'b1; 
				tx_data_out <= {4'd3,temp_in[3:0]};			 
			end
			else if(cnt_uart == 24'd11_099_999 ) begin //温度.低位 
				tx_data_valid <= 1'b1; 
				tx_data_out <= {4'd3,4'b0};
			end 
			else if(cnt_uart == 24'd11_599_999 ) begin //"C"
				tx_data_valid <= 1'b1; 
				tx_data_out <= 8'd67;
			end 
			else if(cnt_uart == 24'd11_999_999 ) begin //换行
				tx_data_valid <= 1'b1; 
				tx_data_out <= 8'd10;
			end
			else begin 
				tx_data_valid <= 1'b0; tx_data_out <= tx_data_out;
			end
			end else begin
				tx_data_valid <= 1'b0; tx_data_out <= tx_data_out;
			end
		end
	end
endmodule

（3）uart_bus.v。

// **************************************************************
// File name	:  uart_bus
// Module name	:  Uart_Bus
//
// Author		:  STEP 
// Date			:  2023/3/31 
// Version		:  V 1.0 
// Description	:  uart串口的顶层模块。
// 
// Modification history
//--------------------------------------------------------------------------
// $Log$
//
// *********************************************************************

module Uart_Bus #
(
parameter				BPS_PARA = 1250 	//12MHz时钟时参数1250对应9600的波特率
)
(
input					clk,			//系统时钟 12MHz
input					rst_n,			//系统复位，低有效

input					uart_rx,		//UART接收输入
output					rx_data_valid,	//接收数据有效脉冲
output			[7:0]	rx_data_out,	//接收到的数据

input					tx_data_valid,	//发送数据有效脉冲
input			[7:0]	tx_data_in,		//要发送的数据
output					uart_tx			//UART发送输出
);	
	
/////////////////////////////////UART接收功能模块例化////////////////////////////////////

wire					bps_en_rx,bps_clk_rx;

//UART接收波特率时钟控制模块 例化
Baud #
(
.BPS_PARA				(BPS_PARA		)
)
Baud_rx
(	
.clk					(clk			),	//系统时钟 12MHz
.rst_n					(rst_n			),	//系统复位，低有效
.bps_en					(bps_en_rx		),	//接收时钟使能
.bps_clk				(bps_clk_rx		)	//接收时钟输出
);

//UART接收数据模块 例化
Uart_Rx Uart_Rx_uut
(
.clk					(clk			),	//系统时钟 12MHz
.rst_n					(rst_n			),	//系统复位，低有效

.bps_en					(bps_en_rx		),	//接收时钟使能
.bps_clk				(bps_clk_rx		),	//接收时钟输入

.uart_rx				(uart_rx		),	//UART接收输入
.rx_data_valid			(rx_data_valid	),	//接收数据有效脉冲
.rx_data_out			(rx_data_out	)	//接收到的数据
);
	
/////////////////////////////////UART发送功能模块例化////////////////////////////////////
wire					bps_en_tx,bps_clk_tx;

//UART发送波特率时钟控制模块 例化
Baud #
(
.BPS_PARA				(BPS_PARA		)
)
Baud_tx
(
.clk					(clk			),	//系统时钟 12MHz
.rst_n					(rst_n			),	//系统复位，低有效
.bps_en					(bps_en_tx		),	//发送时钟使能
.bps_clk				(bps_clk_tx		)	//发送时钟输出
);

//UART发送数据模块 例化
Uart_Tx Uart_Tx_uut
(
.clk					(clk			),	//系统时钟 12MHz
.rst_n					(rst_n			),	//系统复位，低有效

.bps_en					(bps_en_tx		),	//发送时钟使能
.bps_clk				(bps_clk_tx		),	//发送时钟输入

.tx_data_valid			(tx_data_valid	),	//发送数据有效脉冲
.tx_data_in				(tx_data_in		),	//要发送的数据
.uart_tx				(uart_tx		)	//UART发送输出
);

endmodule

（4）uart_r。

// **************************************************************
// File name	:  uart_r
// Module name	:  Uart_Rx
//
// Author		:  STEP 
// Date			:  2023/3/31 
// Version		:  V 1.0 
// Description	:  uart串口的接收模块。
// 
// Modification history
//--------------------------------------------------------------------------
// $Log$
//
// *********************************************************************

module Uart_Rx
(
input					clk,			//系统时钟 12MHz
input					rst_n,			//系统复位，低有效

output	reg				bps_en,			//接收时钟使能
input					bps_clk,		//接收时钟输入

input					uart_rx,		//UART接收输入
output	reg				rx_data_valid,	//接收数据有效脉冲
output	reg		[7:0]	rx_data_out		//接收到的数据
);	

reg	uart_rx0,uart_rx1,uart_rx2;	
//多级延时锁存去除亚稳态
always @ (posedge clk) begin
	uart_rx0 <= uart_rx;
	uart_rx1 <= uart_rx0;
	uart_rx2 <= uart_rx1;
end

//检测UART接收输入信号的下降沿
wire	neg_uart_rx = uart_rx2 & ~uart_rx1;	
		
reg				[3:0]	num;			
//接收时钟使能信号的控制
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n)
		bps_en <= 1'b0;
	else if(neg_uart_rx && (!bps_en))	//当空闲状态（bps_en为低电平）时检测到UART接收信号下降沿，进入工作状态（bps_en为高电平），控制时钟模块产生接收时钟
		bps_en <= 1'b1;		
	else if(num==4'd9)		            //当完成一次UART接收操作后，退出工作状态，恢复空闲状态
		bps_en <= 1'b0;			
end

reg				[7:0]	rx_data;
//当处于工作状态中时，按照接收时钟的节拍获取数据
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		num <= 4'd0;
		rx_data <= 8'd0;
	end else if(bps_en) begin	
		if(bps_clk) begin			
			num <= num + 1'b1;
			if(num<=4'd8) rx_data[num-1] <= uart_rx1; //先接受低位再接收高位，8位有效数据
		end else if(num == 4'd9) begin		          //完成一次UART接收操作后，将获取的数据输出
			num <= 4'd0;				
		end
	end else begin
		num <= 4'd0;
	end
end

//将接收的数据输出，同时控制输出有效信号产生脉冲
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		rx_data_out <= 8'd0;
		rx_data_valid <= 1'b0;
	end else if(num == 4'd9) begin	
		rx_data_out <= rx_data;
		rx_data_valid <= 1'b1;
	end else begin
		rx_data_out <= rx_data_out;
		rx_data_valid <= 1'b0;
	end
end

endmodule

（5）uart_s.v。

// **************************************************************
// File name	:  uart_s
// Module name	:  Uart_Tx
//
// Author		:  STEP 
// Date			:  2023/3/31 
// Version		:  V 1.0 
// Description	:  uart串口的发送模块。
// 
// Modification history
//--------------------------------------------------------------------------
// $Log$
//
// *********************************************************************

module Uart_Tx
(
input					clk,			//系统时钟 12MHz
input					rst_n,			//系统复位，低有效

output	reg				bps_en,			//发送时钟使能
input					bps_clk,		//发送时钟输入

input					tx_data_valid,	//发送数据有效脉冲
input			[7:0]	tx_data_in,		//要发送的数据
output	reg				uart_tx			//UART发送输出
);

reg				[3:0]	num;
reg				[9:0]	tx_data_r;	//融合了起始位和停止位的数据
//驱动发送数据操作
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		bps_en <= 1'b0;
		tx_data_r <= 10'd0;
	end else if(tx_data_valid && (!bps_en))begin	
		bps_en <= 1'b1;		//当检测到接收时钟使能信号的下降沿，表明接收完成，需要发送数据，使能发送时钟使能信号
		tx_data_r <= {1'b1,tx_data_in,1'b0};	
	end else if(num==4'd10) begin	
		bps_en <= 1'b0;		//一次UART发送需要10个时钟信号，然后结束
	end
end

//当处于工作状态中时，按照发送时钟的节拍发送数据
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		num <= 1'b0;
		uart_tx <= 1'b1;
	end else if(bps_en) begin
		if(bps_clk) begin
			num <= num + 1'b1;
			uart_tx <= tx_data_r[num];
		end else if(num>=4'd10) begin
			num <= 4'd0;	
		end
	end
end

endmodule

（6）Baud.v。

// **************************************************************
// File name	:  Baud
// Module name	:  Baud
//
// Author		:  STEP 
// Date			:  2023/3/31 
// Version		:  V 1.0 
// Description	:  产生波特率节拍，给uart发送和接收模块产生相应的波特率节拍信号。
// 
// Modification history
//--------------------------------------------------------------------------
// $Log$
//
// *********************************************************************

module Baud #
(
parameter				BPS_PARA = 1250 //12MHz时钟时参数1250对应9600的波特率
)
(
input					clk,		//系统时钟
input					rst_n,		//系统复位，低有效
input					bps_en,		//接收或发送时钟使能
output	reg				bps_clk		//接收或发送时钟输出
);	

reg				[12:0]	cnt;
//计数器计数满足波特率时钟要求
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) 
		cnt <= 1'b0;
	else if((cnt >= BPS_PARA-1)||(!bps_en)) //当时钟信号不使能（bps_en为低电平）时，计数器清零并停止计数
		cnt <= 1'b0;	                    //当时钟信号使能时，计数器对系统时钟计数，周期为BPS_PARA个系统时钟周期
	else 
		cnt <= cnt + 1'b1;
end
	
//产生相应波特率的时钟节拍，接收模块将以此节拍进行UART数据接收
always @ (posedge clk or negedge rst_n) begin
	if(!rst_n) 
		bps_clk <= 1'b0;
	else if(cnt == (BPS_PARA>>1)) //右移一位等于除以2，终值BPS_PARA为数据更替点，中值数据稳定，做采样点
		bps_clk <= 1'b1;	
	else 
		bps_clk <= 1'b0;
end

endmodule

（7）temppreture.v。

// **************************************************************
// File name	:  tempreture
// Module name	:  DS18B20Z
//
// Author		:  STEP 
// Date			:  2023/3/31 
// Version		:  V 1.0 
// Description	:  温度采集模块，负责FPGA与DS18B20的通讯。
// 
// Modification history
//--------------------------------------------------------------------------
// $Log$
//
// *********************************************************************

module DS18B20Z
(
	input				clk,			// system clock
	input				rst_n,			// system reset, active low
	inout				one_wire,		// ds18b20z one-wire-bus
	output	reg	[15:0]	data_out		// ds18b20z data_out
);
	
	localparam	IDLE	=	3'd0;
	localparam	MAIN	=	3'd1;
	localparam	INIT	=	3'd2;
	localparam	WRITE	=	3'd3;
	localparam	READ	=	3'd4;
	localparam	DELAY	=	3'd5;
	
	//generate clk_1mhz clock
	reg					clk_1mhz;
	reg		[2:0]		cnt_1mhz;
	always@(posedge clk or negedge rst_n) begin
		if(!rst_n) begin
			cnt_1mhz <= 3'd0;
			clk_1mhz <= 1'b0;
		end else if(cnt_1mhz >= 3'd5) begin
			cnt_1mhz <= 3'd0;
			clk_1mhz <= ~clk_1mhz;
		end else begin
			cnt_1mhz <= cnt_1mhz + 1'b1;
		end
	end
	
	reg					one_wire_buffer;
	reg		[3:0]		cnt_main;
	reg		[7:0]		data_wr;
	reg		[7:0]		data_wr_buffer;
	reg		[2:0]		cnt_init;
	reg		[19:0]		cnt_delay;
	reg		[19:0]		num_delay;
	reg		[5:0]		cnt_write;
	reg		[5:0]		cnt_read;
	reg		[15:0]		temperature;
	reg		[7:0]		temperature_buffer;
	reg		[2:0] 		state = IDLE;
	reg		[2:0] 		state_back = IDLE;
	always@(posedge clk_1mhz or negedge rst_n) begin
		if(!rst_n) begin
			state <= IDLE;
			state_back <= IDLE;
			cnt_main <= 4'd0;
			cnt_init <= 3'd0;
			cnt_write <= 6'd0;
			cnt_read <= 6'd0;
			cnt_delay <= 20'd0;
			one_wire_buffer <= 1'bz;
			temperature <= 16'h0;
		end else begin
			case(state)
				IDLE:begin
						state <= MAIN;
						state_back <= MAIN;
						cnt_main <= 4'd0;
						cnt_init <= 3'd0;
						cnt_write <= 6'd0;
						cnt_read <= 6'd0;
						cnt_delay <= 20'd0;
						one_wire_buffer <= 1'bz;
					end
				MAIN:begin
						if(cnt_main >= 4'd11) cnt_main <= 1'b0;
						else cnt_main <= cnt_main + 1'b1;
						case(cnt_main)
							4'd0: begin state <= INIT; end
							4'd1: begin data_wr <= 8'hcc;state <= WRITE; end
							4'd2: begin data_wr <= 8'h44;state <= WRITE; end
							4'd3: begin num_delay <= 20'd750000;state <= DELAY;state_back <= MAIN; end
							
							4'd4: begin state <= INIT; end
							4'd5: begin data_wr <= 8'hcc;state <= WRITE; end
							4'd6: begin data_wr <= 8'hbe;state <= WRITE; end
							
							4'd7: begin state <= READ; end
							4'd8: begin temperature[7:0] <= temperature_buffer; end
							
							4'd9: begin state <= READ; end
							4'd10: begin temperature[15:8] <= temperature_buffer; end
							
							4'd11: begin state <= IDLE;data_out <= temperature; end
							default: state <= IDLE;
						endcase
					end
				INIT:begin
						if(cnt_init >= 3'd6) cnt_init <= 1'b0;
						else cnt_init <= cnt_init + 1'b1;
						case(cnt_init)
							3'd0: begin one_wire_buffer <= 1'b0; end
							3'd1: begin num_delay <= 20'd500;state <= DELAY;state_back <= INIT; end
							3'd2: begin one_wire_buffer <= 1'bz; end
							3'd3: begin num_delay <= 20'd100;state <= DELAY;state_back <= INIT; end
							3'd4: begin if(one_wire) state <= IDLE; else state <= INIT; end
							3'd5: begin num_delay <= 20'd400;state <= DELAY;state_back <= INIT; end
							3'd6: begin state <= MAIN; end
							default: state <= IDLE;
						endcase
					end
				WRITE:begin
						if(cnt_write >= 6'd50) cnt_write <= 1'b0;
						else cnt_write <= cnt_write + 1'b1;
						case(cnt_write)
							//lock data_wr
							6'd0: begin data_wr_buffer <= data_wr; end
							//write bit 0
							6'd1: begin one_wire_buffer <= 1'b0; end
							6'd2: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd3: begin one_wire_buffer <= data_wr_buffer[0]; end
							6'd4: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd5: begin one_wire_buffer <= 1'bz; end
							6'd6: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 1
							6'd7: begin one_wire_buffer <= 1'b0; end
							6'd8: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd9: begin one_wire_buffer <= data_wr_buffer[1]; end
							6'd10: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd11: begin one_wire_buffer <= 1'bz; end
							6'd12: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 2
							6'd13: begin one_wire_buffer <= 1'b0; end
							6'd14: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd15: begin one_wire_buffer <= data_wr_buffer[2]; end
							6'd16: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd17: begin one_wire_buffer <= 1'bz; end
							6'd18: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 3
							6'd19: begin one_wire_buffer <= 1'b0; end
							6'd20: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd21: begin one_wire_buffer <= data_wr_buffer[3]; end
							6'd22: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd23: begin one_wire_buffer <= 1'bz; end
							6'd24: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 4
							6'd25: begin one_wire_buffer <= 1'b0; end
							6'd26: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd27: begin one_wire_buffer <= data_wr_buffer[4]; end
							6'd28: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd29: begin one_wire_buffer <= 1'bz; end
							6'd30: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 5
							6'd31: begin one_wire_buffer <= 1'b0; end
							6'd32: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd33: begin one_wire_buffer <= data_wr_buffer[5]; end
							6'd34: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd35: begin one_wire_buffer <= 1'bz; end
							6'd36: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 6
							6'd37: begin one_wire_buffer <= 1'b0; end
							6'd38: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd39: begin one_wire_buffer <= data_wr_buffer[6]; end
							6'd40: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd41: begin one_wire_buffer <= 1'bz; end
							6'd42: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//write bit 7
							6'd43: begin one_wire_buffer <= 1'b0; end
							6'd44: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							6'd45: begin one_wire_buffer <= data_wr_buffer[7]; end
							6'd46: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd47: begin one_wire_buffer <= 1'bz; end
							6'd48: begin num_delay <= 20'd2;state <= DELAY;state_back <= WRITE; end
							//back to main
							6'd49: begin num_delay <= 20'd80;state <= DELAY;state_back <= WRITE; end
							6'd50: begin state <= MAIN; end
							default: state <= IDLE;
						endcase
					end
				READ:begin
						if(cnt_read >= 6'd48) cnt_read <= 1'b0;
						else cnt_read <= cnt_read + 1'b1;
						case(cnt_read)
							//read bit 0
							6'd0: begin one_wire_buffer <= 1'b0; end
							6'd1: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd2: begin one_wire_buffer <= 1'bz; end
							6'd3: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd4: begin temperature_buffer[0] <= one_wire; end
							6'd5: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 1
							6'd6: begin one_wire_buffer <= 1'b0; end
							6'd7: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd8: begin one_wire_buffer <= 1'bz; end
							6'd9: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd10: begin temperature_buffer[1] <= one_wire; end
							6'd11: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 2
							6'd12: begin one_wire_buffer <= 1'b0; end
							6'd13: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd14: begin one_wire_buffer <= 1'bz; end
							6'd15: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd16: begin temperature_buffer[2] <= one_wire; end
							6'd17: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 3
							6'd18: begin one_wire_buffer <= 1'b0; end
							6'd19: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd20: begin one_wire_buffer <= 1'bz; end
							6'd21: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd22: begin temperature_buffer[3] <= one_wire; end
							6'd23: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 4
							6'd24: begin one_wire_buffer <= 1'b0; end
							6'd25: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd26: begin one_wire_buffer <= 1'bz; end
							6'd27: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd28: begin temperature_buffer[4] <= one_wire; end
							6'd29: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 5
							6'd30: begin one_wire_buffer <= 1'b0; end
							6'd31: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd32: begin one_wire_buffer <= 1'bz; end
							6'd33: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd34: begin temperature_buffer[5] <= one_wire; end
							6'd35: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 6
							6'd36: begin one_wire_buffer <= 1'b0; end
							6'd37: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd38: begin one_wire_buffer <= 1'bz; end
							6'd39: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd40: begin temperature_buffer[6] <= one_wire; end
							6'd41: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//read bit 7
							6'd42: begin one_wire_buffer <= 1'b0; end
							6'd43: begin num_delay <= 20'd2;state <= DELAY;state_back <= READ; end
							6'd44: begin one_wire_buffer <= 1'bz; end
							6'd45: begin num_delay <= 20'd10;state <= DELAY;state_back <= READ; end
							6'd46: begin temperature_buffer[7] <= one_wire; end
							6'd47: begin num_delay <= 20'd55;state <= DELAY;state_back <= READ; end
							//back to main
							6'd48: begin state <= MAIN; end
							default: state <= IDLE;
						endcase
					end
				DELAY:begin
						if(cnt_delay >= num_delay) begin
							cnt_delay <= 1'b0;
							state <= state_back; 
						end else cnt_delay <= cnt_delay + 1'b1;
					end
			endcase
		end
	end
	
	assign	one_wire = one_wire_buffer;
	
endmodule

（8）bin_to_bcd.v。

// **************************************************************
// File name	:  bin_to_bcd
// Module name	:  bcd_8421
//
// Author		:  STEP 
// Date			:  2023/3/31 
// Version		:  V 1.0 
// Description	:  二进制转换为BCD码。
// 
// Modification history
//--------------------------------------------------------------------------
// $Log$
//
// *********************************************************************

module bin_to_bcd #
(
parameter B_SIZE = 21
)
(
input						rst_n,			// system reset, active low
input		[B_SIZE-1:0]	bin_code,		// binary code
output	reg	[B_SIZE+3:0]	bcd_code		// bcd code
);

reg		[2*B_SIZE+3:0]		shift_reg;   
always@(bin_code or rst_n)begin      
	shift_reg= {25'h0,bin_code};          
	if(!rst_n) bcd_code <= 0;      
	else begin         
		repeat(B_SIZE)//repeat B_SIZE times
			begin                                
				if (shift_reg[24:21] >= 5) shift_reg[24:21] = shift_reg[24:21] + 2'b11;
				if (shift_reg[28:25] >= 5) shift_reg[28:25] = shift_reg[28:25] + 2'b11;
				if (shift_reg[32:29] >= 5) shift_reg[32:29] = shift_reg[32:29] + 2'b11;
				if (shift_reg[36:33] >= 5) shift_reg[36:33] = shift_reg[36:33] + 2'b11;
				if (shift_reg[40:37] >= 5) shift_reg[40:37] = shift_reg[40:37] + 2'b11;
				if (shift_reg[44:41] >= 5) shift_reg[44:41] = shift_reg[44:41] + 2'b11;
				shift_reg = shift_reg << 1; 
			end         
		bcd_code<=shift_reg[45:21];   
	end  
end

endmodule