3.1.3 Verilog HDL建模描述

（1）外部时钟驱动RGB LED。

module led(
input  sys_clk,
output [2:0] RGB_led
);
reg    [23:0]  cnt_clk_1s = 1'b0   ;
reg            clk_1s     = 1'b0   ;
reg    [2:0]   cnt_led    = 1'b0   ; 

always@ (posedge sys_clk)begin
    if(cnt_clk_1s==24'd1200_0000)begin
        cnt_clk_1s <= 1'b0;
        clk_1s     <= ~clk_1s;
    end
    else begin
        cnt_clk_1s <= cnt_clk_1s+1'b1;
        clk_1s<=clk_1s;
    end
end

always@(posedge clk_1s )begin
    if(cnt_led==3'b111)
        cnt_led<=1'b0;
    else
        cnt_led<=cnt_led+1'b1;
end
assign RGB_led = cnt_led;
endmodule

（2）内部时钟驱动RGB LED。

module led(
output [2:0] RGB_led
);
reg    [23:0]  cnt_clk_1s = 1'b0   ;
reg            clk_1s     = 1'b0   ;
reg    [2:0]   cnt_led    = 1'b0   ; 
wire  sys_clk;
//内部12M时钟
HSOSC #(
.CLKHF_DIV ("0b10")//0b00 = 48 MHz, 0b01 = 24 MHz, 0b10 = 12 MHz, 0b11 = 6 MHz
) OSCInst0 ( 
.CLKHFEN (1'b1   ), 
.CLKHFPU (1'b1   ), 
.CLKHF   (sys_clk)
);

always@ (posedge sys_clk)begin
    if(cnt_clk_1s==24'd599_0000)begin
        cnt_clk_1s <= 1'b0;
        clk_1s     <= ~clk_1s;
    end
    else begin
        cnt_clk_1s <= cnt_clk_1s+1'b1;
        clk_1s<=clk_1s;
    end
end

always@(posedge clk_1s )begin
    if(cnt_led==3'b111)
        cnt_led<=1'b0;
    else
        cnt_led<=cnt_led+1'b1;
end
assign RGB_led = cnt_led;
endmodule    else
        cnt_led<=cnt_led+1'b1;
end
assign RGB_led = cnt_led;
endmodule