Category Identifer Names Definition Example Can contain any letter, digit, underscore , or \$ Can not begin with a digit or be a keyword Case sensitive |q0 Primenumber lteflg

Signal Values 0 = logic value 0 1 = logic value 1 z or Z = high impedance x or X = unknown value Numbers d = decimal b = binary h = hexadecimal o = octal

35 (default decimal) 4‘b1001 8’a5 = 8’b10100101 Parameters Associates an identifer name with a value that can be overridden with the defparam statement

#(parameter N = 8) Local parameters Associates an identifer name with a constant that cannot be directly overridden localparam [1:0] s0 = 2’b00, s1 = 2’b01, s2 = 2’b10; Nets and Variables Types wire (used to connect one logic element to another) reg (variables assigned values in always block) integer (useful for loop control variables) wire [3:0] d; wire led; reg [7:0] q; integer k; Module module modulename [#(parameterportlist)] (portdirtypename,{ portdirtype_name } ); [wire declarations] [reg declarations] [assign assignments] [always blocks] endmodule module register #(parameter N = 8) (input wire load , input wire clk , input wire clr , input wire [N-1:0] d , output reg [N-1:0] q ); always @(posedge clk or posedge clr) if(clr == 1) q ⇐ 0; else if(load) q ⇐ d; endmodule Logic operators ~ (NOT) & (AND)

~(&) (NAND) ~(|) (NOR)

(XOR) ~

assign z = ~y; assign c = a & b; assign z = x | y; assign w = ~(u & v); assign r = ~(s | t); assign z = x ^ y; assign d = a ~^ b; Reduction operators & (AND)

~& (NAND) ~| (NOR)

(XOR) ~

assign c = &a; assign z = |y; assign w = ~&v; assign r = ~|t; assign z = ^y; assign d = ~^b; Arithmetic operators + (addition) - (subtraction) * (multiplication) / (division) % (mod) count ⇐ count + 1; q ⇐ q – 1;