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analog_discovery_2_参考手册 [2016/05/31 13:35]
admin
analog_discovery_2_参考手册 [2017/03/28 02:57] (当前版本)
gongyu [9.10. Other features]
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 The Analog Discovery 2 was designed for students in typical university-based circuits and electronics classes. Its features and specifications,​ as well as the additional requirements of operating from USB or external power, maintaining the small and portable form factor, the robustness to withstand student use in a variety of environments,​ and low-cost are based directly on feedback that was obtained from numerous professors from several universities. Meeting all of these requirements proved challenging;​ however, the task ultimately generated some new and innovative circuits. This document describes the Analog Discovery 2's circuits, with the intent of providing a better understanding of its electrical functions, operations, and a more detailed description of the hardware’s features and limitations. It is not intended to provide enough information to enable complete duplication of the Analog Discovery 2, or to allow users to design custom configurations for programmable parts in the design. The Analog Discovery 2 was designed for students in typical university-based circuits and electronics classes. Its features and specifications,​ as well as the additional requirements of operating from USB or external power, maintaining the small and portable form factor, the robustness to withstand student use in a variety of environments,​ and low-cost are based directly on feedback that was obtained from numerous professors from several universities. Meeting all of these requirements proved challenging;​ however, the task ultimately generated some new and innovative circuits. This document describes the Analog Discovery 2's circuits, with the intent of providing a better understanding of its electrical functions, operations, and a more detailed description of the hardware’s features and limitations. It is not intended to provide enough information to enable complete duplication of the Analog Discovery 2, or to allow users to design custom configurations for programmable parts in the design.
  
-==== Pinout Diagram ​====+==== 连线图 ​====
 {{ :​analogdiscovery2-pinout-600.png?​nolink&​450 |Analog Discovery 2 Pinout.}} {{ :​analogdiscovery2-pinout-600.png?​nolink&​450 |Analog Discovery 2 Pinout.}}
  
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 ---- ----
-====== 2. Scope ======+====== 2. 示波器 ​======
  
 //​**Important Note**: Unlike traditional inexpensive scopes, the Analog Discovery 2 inputs are fully differential. However, a GND connection to the circuit under test is needed to provide a stable common mode voltage. The Analog Discovery 2 GND reference is connected to the USB GND. Depending on the PC powering scheme, and other PC connections (Ethernet, audio, etc. – which might also be grounded) the Analog Discovery 2 GND reference might be connected to the whole GND system and ultimately to the power network protection (earth ground). The circuit under test might also be connected to earth or  possibly floating. For safety reasons, it is the user’s responsibility to understand the powering and grounding scheme and make sure that there is a common GND reference between the Analog Discovery 2 and the circuit under test, and that the common mode and differential voltages do not exceed the limits shown in equation \ref{1}. Furthermore,​ for distortion-free measurements,​ the common mode and differential voltages need to fit into the linear range shown in Figs. [[analog_discovery_2:​refmanual#​figure_12|12]] and [[analog_discovery_2:​refmanual#​figure_13|13]]. //​**Important Note**: Unlike traditional inexpensive scopes, the Analog Discovery 2 inputs are fully differential. However, a GND connection to the circuit under test is needed to provide a stable common mode voltage. The Analog Discovery 2 GND reference is connected to the USB GND. Depending on the PC powering scheme, and other PC connections (Ethernet, audio, etc. – which might also be grounded) the Analog Discovery 2 GND reference might be connected to the whole GND system and ultimately to the power network protection (earth ground). The circuit under test might also be connected to earth or  possibly floating. For safety reasons, it is the user’s responsibility to understand the powering and grounding scheme and make sure that there is a common GND reference between the Analog Discovery 2 and the circuit under test, and that the common mode and differential voltages do not exceed the limits shown in equation \ref{1}. Furthermore,​ for distortion-free measurements,​ the common mode and differential voltages need to fit into the linear range shown in Figs. [[analog_discovery_2:​refmanual#​figure_12|12]] and [[analog_discovery_2:​refmanual#​figure_13|13]].
  
 For those applications which scope GND cannot be the USB ground, a USB isolation solution, such as what is described in ADI’s [[http://​www.analog.com/​en/​circuits-from-the-lab/​CN0160/​vc.html|CN-0160]] can be used; however, this will limit things to USB full speed (12 Mbps), and will impact the update rate (screen refresh rates, not sample rates) of the Analog Discovery 2.// For those applications which scope GND cannot be the USB ground, a USB isolation solution, such as what is described in ADI’s [[http://​www.analog.com/​en/​circuits-from-the-lab/​CN0160/​vc.html|CN-0160]] can be used; however, this will limit things to USB full speed (12 Mbps), and will impact the update rate (screen refresh rates, not sample rates) of the Analog Discovery 2.//
-===== 2.1. Scope Input Divider and Gain Selection ​=====+===== 2.1. 示波器输入分压及增益选择 ​=====
  
 [[analog_discovery_2:​refmanual#​figure_3|Figure 3]] shows the scope input divider and gain selection stage. [[analog_discovery_2:​refmanual#​figure_3|Figure 3]] shows the scope input divider and gain selection stage.
  
-Two symmetrical ​R-C dividers provide+两个对称的R-C分压电路提供了
-  * Scope input impedance ​= 1MOhm || 24pF +  * 示波器输入阻抗 ​= 1MOhm || 24pF 
-  * Two different attenuations for high-gain/​low-gain ​(10:1) +  * 两个不同的衰减用于高增益/低增益(10:1) 
-  * Controlled capacitancemuch higher than the parasitical capacitance of subsequent stages +  * 可控的电容比后级的杂散电容要高很多 
-  * Constant attenuation and high CMMR over a large frequency range (trimmer adjusted+  * 在大频率范围保持常数衰减以及高的CMMR(通过调整
-  * Protection for overvoltage ​(with the ESD diodes of the ADG612 inputs) +  * 过压保护(在ADG612输入端有ESD二极管)
- +
-The maximum voltage rating for scope inputs is limited by C1 thru C24 to:+
  
 +受限于C1到C24,示波器输入的最大电压范围为:​
 $$-50V<​V_{inP},​V_{inN}<​50V\label{1}\tag{1}$$ $$-50V<​V_{inP},​V_{inN}<​50V\label{1}\tag{1}$$
  
-The maximum swing of the input signal to avoid signal distortion by opening the ADG612 ESD diodes is (for both low-gain and high-gain): +为避免信号失真讲ADG612ESD二极管开路导致的输入信号的最大摆动幅度:(对于低增益和高增益都适用): 
  
 $$-26V<​V_{inP},​V_{inN}<​26V\label{2}\tag{2}$$ $$-26V<​V_{inP},​V_{inN}<​26V\label{2}\tag{2}$$
  
-An analog switch ​([[http://​www.analog.com/​en/​switchesmultiplexers/​analog-switches/​adg612/​products/​product.html|ADG612]]) ​allows selecting high-gain versus low-gain ​(EN_HG_SC1, EN_LG_SC1) ​signals from the FPGA. The and branches of the differential path are switched together. ​+模拟开关([[http://​www.analog.com/​en/​switchesmultiplexers/​analog-switches/​adg612/​products/​product.html|ADG612]])允许通过FPGA的信号(EN_HG_SC1, EN_LG_SC1)来选择高增益或者低增益。差分路径的PN支路都一起切换。
  
-The ADG612 ​quad switch was used because it provides excellent impedance and bandwidth parameters+采用具有4路开关的ADG612主要是因为它能够提供优秀的阻抗和带宽参数
-  * 1 pC charge injection ​ +  * 1pC电荷注入 ​ 
-  * ±2.7 V to ±5.5 V dual-supply operation ​ +  * ±2.7V到±5.5V双电压供电 ​ 
-  * 100 pA maximum at 25°C leakage currents ​ +  * 25°C时最大100pA的泄漏电流 ​ 
-  * 85 Ω on resistance ​ +  * 85Ωon阻抗 ​ 
-  * Rail-to-rail switching operation ​ +  * 轨到轨的开关工作 ​ 
-  * Typical power consumption: <0.1 μW  +  * 典型功耗: <0.1 μW  
-  * TTL-/CMOS-compatible inputs ​ +  * 输入TTL-/CMOS兼容 ​ 
-  * -3 dB Bandwidth ​680 MHz  +  * -3dB带宽680 MHz  
-  * 5 pF each of CS, CD (ON or OFF) +  * 每个CS, CD (ON or OFF) 5pF
  
-The low gain is: $$\frac {V_{mux}}{V_{in}}=\frac {R_6}{R_1+R_4+R_6}=0.019\label{3}\tag{3}$$+低增益为: $$\frac {V_{mux}}{V_{in}}=\frac {R_6}{R_1+R_4+R_6}=0.019\label{3}\tag{3}$$
  
-The low gain is used for input voltages: ​$$| V_{indiff} | = | V_{inP}-V_{inN} |<​50V\label{4}\tag{4}$$+低增益用于输入电压为:$$| V_{indiff} | = | V_{inP}-V_{inN} |<​50V\label{4}\tag{4}$$
  
-The high gain is: $$\frac {V_{mux}}{V_{in}} = \frac {R_4 + R_6}{R_1 + R_4 + R_6} = 0.212 \label{5}\tag{5}$$+高增益为:$$\frac {V_{mux}}{V_{in}} = \frac {R_4 + R_6}{R_1 + R_4 + R_6} = 0.212 \label{5}\tag{5}$$
  
-The high gain is used for input voltages: $$|V_{indiff}| = |V_{inP} - V_{inN}|<​7V \label{6}\tag{6}$$+高增益用于输入电压为: $$|V_{indiff}| = |V_{inP} - V_{inN}|<​7V \label{6}\tag{6}$$
  
-{{ :​analog_discovery_figure_3.png |Figure 3. Input divider and gain selection.}} +{{ :​analog_discovery_figure_3.png |Figure 3. 输入分压合增益选择}} 
-<WRAP centeralign>​ ** 图3. Input divider and gain selection.** </​WRAP>​+<WRAP centeralign>​ ** 图3.输入分压合增益选择** </​WRAP>​
  
-===== 2.2. Scope Buffer ​=====+===== 2.2. 示波器缓冲 ​=====
  
-A non-inverting OpAmp stage provides very high impedance as load for the input divider ​[[analog_discovery_2:​refmanual#​figure_4|(Fig. 4)]]. +一级同相运放提供了非常高的阻抗作为输入分压电路的负载 ​[[analog_discovery_2:​refmanual#​figure_4|(Fig. 4)]]. 
  
 {{ :​analog_discovery_figure_4.png |Figure 4. Scope buffer.}} {{ :​analog_discovery_figure_4.png |Figure 4. Scope buffer.}}
 +<WRAP centeralign>​ 图4 示波器缓冲</​WRAP>​
  
-The useful features of the [[http://​www.analog.com/​en/​high-speed-op-amps/​fet-input-amplifiers/​ad8066/​products/​product.html|AD8066]] ​are+[[http://​www.analog.com/​en/​high-speed-op-amps/​fet-input-amplifiers/​ad8066/​products/​product.html|AD8066]]有用的特性有
-  * FET input amplifier ​ +  * FET输入放大器 
-  * 1 pA input bias current ​ +  * 1pA输入偏置电流 ​ 
-  * Low cost  +  * 低成本 ​ 
-  * High speed145 MHz, −3 dB bandwidth ​(G = +1)  +  * 高速145MHz, −3dB带宽(G = +1)  
-  * 180 V/μs slew rate (G = +2)  +  * 180V/μs摆率(G = +2)  
-  * Low noise 7 nV/√Hz (f = 10 kHz), 0.6 fA/√Hz (f = 10 kHz)  +  * 低噪声7nV/√Hz (f = 10 kHz), 0.6 fA/√Hz (f = 10 kHz)  
-  * Wide supply voltage range5 V to 24 V  +  * 较宽的供电电压范围5V - 24 V  
-  * Rail-to-rail output ​ +  * 轨到轨输出 ​ 
-  * Low offset voltage ​1.5 mV maximum ​ +  * 低偏置电压:最大1.5mV  
-  * Excellent distortion specifications ​+  * 极优秀的失真指标 ​
   * SFDR −88 dBc @ 1 MHz    * SFDR −88 dBc @ 1 MHz 
-  * Low power: 6.4 mA/​amplifier typical supply current ​ +  * 低功耗每个放大器的典型供电电流为6.4mA  
-  * Small packaging: MSOP-8 +  * 小封装: MSOP-8
  
-Resistors and capacitors in the figure help to maximize the bandwidth and reduce peaking ​(which might be significant at unity gain).+图中的电阻和电容帮助最大化带宽并减低峰值(在跟随的状态时可能非常剧烈).
  
 The [[http://​www.analog.com/​en/​high-speed-op-amps/​fet-input-amplifiers/​ad8066/​products/​product.html|AD8066]] is supplied ± 5.5V.  The [[http://​www.analog.com/​en/​high-speed-op-amps/​fet-input-amplifiers/​ad8066/​products/​product.html|AD8066]] is supplied ± 5.5V. 
  
-The maximum input voltage swing is: $-5.5V<​V_{mux P},V_{mux N}<​2.2V\label{7}\tag{7}$+最大输入电压摆动: $-5.5V<​V_{mux P},V_{mux N}<​2.2V\label{7}\tag{7}$
  
-The maximum output voltage swing is: $-5.38V<​V_{buf P},V_{buf N}<​5.4V\label{8}\tag{8}$+最大输出电压摆动: $-5.38V<​V_{buf P},V_{buf N}<​5.4V\label{8}\tag{8}$
  
-The gain is: $$\frac {V_{buf}}{V_{mux}}=1\label{9}\tag{9}$$ +增益为: $$\frac {V_{buf}}{V_{mux}}=1\label{9}\tag{9}$$ 
-===== 2.3. Scope Reference and Offset ​=====+===== 2.3. 示波器参考和偏置 ​=====
  
 [[analog_discovery_2:​refmanual#​figure_5|Figure 5]] shows the scope voltage reference sources and offset control stage. A low noise reference is used to generate reference voltages for all the scope stages. Buffered and scaled replicas of the reference voltages are provided for the buffer stages and individually for each scope channel to minimize crosstalk. A dual channel DAC generates the offset voltages, to be added over the input signal, for vertical position. Buffers are used to provide low impedance. [[analog_discovery_2:​refmanual#​figure_5|Figure 5]] shows the scope voltage reference sources and offset control stage. A low noise reference is used to generate reference voltages for all the scope stages. Buffered and scaled replicas of the reference voltages are provided for the buffer stages and individually for each scope channel to minimize crosstalk. A dual channel DAC generates the offset voltages, to be added over the input signal, for vertical position. Buffers are used to provide low impedance.
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-==== 2.6.1. ​Analog Section ​==== +==== 2.6.1. ​模拟部分 ​==== 
  
-The Analog Discovery 2 uses a dual channel, high speed, low power, ​14-bit, 105MSPS ​ADC (Analog part number ​[[http://​www.analog.com/​en/​analog-to-digital-converters/​ad-converters/​ad9648/​products/​product.html|AD9648]]), ​as shown in [[analog_discovery_2:​refmanual#​figure_9|Fig. 9]] .+Analog Discovery 2 采用了双通道、高速、14位、105Msps ​ADC(型号为[[http://​www.analog.com/​en/​analog-to-digital-converters/​ad-converters/​ad9648/​products/​product.html|AD9648]]), ​如图[[analog_discovery_2:​refmanual#​figure_9|9]] .
  
-{{ :​analog_discovery_figure_9.png |Figure ​9. ADC - analog section.}}+{{ :​analog_discovery_figure_9.png |9. ADC-模拟部分.}}
 //​{{anchor:​figure_9:​Figure 9. ADC - analog section.}}//​ //​{{anchor:​figure_9:​Figure 9. ADC - analog section.}}//​
  
-The important features of AD9648:+AD9648的主要性能:
   * SNR = 74.5dBFS @70 MHz   * SNR = 74.5dBFS @70 MHz
   * SFDR =91dBc @70 MHz   * SFDR =91dBc @70 MHz
-  * Low power: 78mW/channel ​ADC core@ 125MSPS +  * 低功耗: 78mW/ADC通道 ​@ 125MSPS 
-  * Differential analog input with 650 MHz bandwidth +  * 650MHz差分模拟输入带宽 
-  * IF sampling frequencies to 200 MHz +  * 中频取样频率到200MHz 
-  * On-chip voltage reference and sample-and-hold circuit +  * 片上电压基准和取样保持电路 
-  * 2 V p-p differential analog input+  * 2Vp-p差分模拟输入
   * DNL = ±0.35 LSB   * DNL = ±0.35 LSB
-  * Serial port control options +  * 可选串行端口控制 
-  * Offset binary, gray codeor two's complement data format +  * 偏移二进制, gray或2的补码数据格式 
-  * Optional clock duty cycle stabilizer +  * 可选的时钟占空比稳定器 
-  * Integer ​1-to-input clock divider +  * 输入时钟可以整数(18)分频 
-  * Data output multiplex option +  * 可选数据输出复用 
-  * Built-in selectable digital test pattern generation +  * 内建可选的数字测试模式发生器 
-  * Energy-saving power-down modes +  * 节能断电模式 
-  * Data clock out with programmable clock and data alignment+  * 可以编程的时钟/数据对齐的数据时钟输出
  
 The differential inputs are driven via a low-pass filter comprised of C141 together with R10 through R13, in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by two for operating at a constant 100 MHz sampling rate. An external reference voltage is used, buffered by IC 19. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage. The differential inputs are driven via a low-pass filter comprised of C141 together with R10 through R13, in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by two for operating at a constant 100 MHz sampling rate. An external reference voltage is used, buffered by IC 19. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage.
  
-The differential input voltage range is:+差分输入电压范围:
  
 $$-1V<​V_{ADC\;​diff}<​1V\label{19}\tag{19}$$ $$-1V<​V_{ADC\;​diff}<​1V\label{19}\tag{19}$$
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 ---- ----
  
-====== 6. Power Supplies and Control ​====== +====== 6. 电源和控制 ​====== 
- +此部分为所有的电源监测和控制电路,内部的电源以及用户电源。
-This block includes all power monitoring and control circuitry, internal power supplies, and user power supplies. ​+
  
  
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   * 1.25A continuous output current   * 1.25A continuous output current
-  * 145 mΩ and 70 mΩ integrated MOSFETs ​+  * 145 mΩ and 70 mΩ integrated MOSFETs ​
   * Input voltage range from 2.3 V to 5.5 V; output voltage from 0.6 V to VIN    * Input voltage range from 2.3 V to 5.5 V; output voltage from 0.6 V to VIN 
   * 1.2 MHz fixed switching frequency; Selectable PWM or PFM mode operation ​   * 1.2 MHz fixed switching frequency; Selectable PWM or PFM mode operation ​
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   * Imax (AUX powered):​ 700mA((This limit results from the structure of each user power supply (positive and negative). It is not conditioned by the load degree of the complementary user supply.)) for each supply   * Imax (AUX powered):​ 700mA((This limit results from the structure of each user power supply (positive and negative). It is not conditioned by the load degree of the complementary user supply.)) for each supply
   * Accuracy (no load):​ ±10mV   * Accuracy (no load):​ ±10mV
-  * Output impedance: 50mΩ (typical)+  * Output impedance: 50mΩ (typical)
  
  
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----- 
- 
-*³The Network Analyzer instrument in WaveForms uses a channel of Analog Outputs (AWG) and all Analog Inputs (Scope) hardware resources. When it starts running, all other instruments using the same HW resources (competing instruments:​ AWG, Scope, Voltmeters, Spectrum Analyzer) are forced to a BUSY state. When running a competing instrument, the Network Analyzer is forced to a BUSY state 
- 
-°This instrument in WaveForms uses Analog Inputs (Scope) Hardware resources competing with other WaveForms instruments (Scope, Spectrum Analyzer, Network Analyzer, Voltmeter). When it starts running, the competing instruments are forced to a BUSY state. When running a competing instrument, this instrument is forced to a BUSY state. ​ 
  
-°°This instrument in WaveForms uses Analog Inputs (Scope) Hardware resources competing with other WaveForms instruments (Scope, Spectrum Analyzer, Network Analyzer, Voltmeter). When it starts running, the competing instruments are forced to a BUSY state. When running a competing instrument, this instrument is forced to a BUSY state.