====38译码器测试文件====
<code verilog>
// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Module: Decode38_test
// 
// Author: Step
// 
// Description: Testbench for Decode38
// 
// Web: www.ecbcamp.com
// 
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Version: |Mod. Date:   |Changes Made:
// V1.0     |2015/11/11   |Initial ver
// --------------------------------------------------------------------
`timescale 1ns / 100ps
module Decode38_test;

reg Enable;
reg [2:0] A_in;
initial
	begin
		Enable = 1'b0;
		A_in = 3'b000;
	end
	
always Enable = #200 ~Enable;
always A_in = #20 $random;

wire [7:0] Y_out;
Decode38 Decode38_uut
(
.Enable(Enable),
.A_in(A_in),
.Y_out(Y_out)
);
	
endmodule
                      
</code>