用于代码风格

<code verilog>

module beeper (
input clk,
input [3:0] key_n,
output speaker
);
 
parameter cnt_Width = 15;
parameter ClkDividerDo = 12000000/262/2;
parameter ClkDividerRe = 12000000/294/2;
parameter ClkDividerMi = 12000000/330/2;
parameter ClkDividerFa = 12000000/349/2;
reg en, beep;
reg [cnt_Width-1:0] cnt, ClkDivider;

always @(*) 
    case(key_n)
        4'b1110: begin ClkDivider = ClkDividerDo; en = 1'b1; end
        4'b1101: begin ClkDivider = ClkDividerRe; en = 1'b1; end
        4'b1011: begin ClkDivider = ClkDividerMi; en = 1'b1; end
        4'b0111: begin ClkDivider = ClkDividerFa; en = 1'b1; end
        default: begin ClkDivider = ClkDivider;   en = 1'b0; end
    endcase

always @(posedge clk) 
    if(cnt >= ClkDivider-1) cnt <= {cnt_Width{1'b0}}; 
    else cnt <= cnt + 1'b1;
 
always @(posedge clk) 
    if(cnt >= ClkDivider-1) beep <= ~beep;
    else beep <= beep;
 
assign speaker = en? beep : 1'b0;

endmodule 


</code>