序列检测设计文件
// --------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------
// Module: Serial_Detect
//
// Author: Step
//
// Description: Serial date detect
//
// Web: www.ecbcamp.com
//
// --------------------------------------------------------------------
// Code Revision History :
// --------------------------------------------------------------------
// Version: |Mod. Date: |Changes Made:
// V1.0 |2015/11/11 |Initial ver
// --------------------------------------------------------------------
module Serial_Detect #
(
parameter CNT_NUM = 12500000
)
(
clk,rst_n,vin,clk_1hz,vout
);
input clk; //system clock
input rst_n; //system reset
input vin; //Serial date input
output reg clk_1hz;
output reg vout; //Serial detect flag output
parameter s0=2'd0,s1=2'd1,s2=2'd2;
reg [24:0] cnt = 25'd0;
//reg clk_1hz = 1'b0;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cnt <= 25'd0;
clk_1hz <= 1'b0;
end else if(cnt>=(CNT_NUM-1)) begin
cnt <= 25'd0;
clk_1hz <= ~clk_1hz;
end else begin
cnt <= cnt + 25'd1;
end
end
//Finite state machine
reg[1:0]state;
always @(posedge clk_1hz or negedge rst_n) begin
if(!rst_n) begin
state<=s0;
vout<=0;
end else case(state)
s0: begin
if(vin==0) begin state<=s0;vout<=0; end
else begin state<=s1;vout<=0; end
end
s1: begin
if(vin==0) begin state<=s2;vout<=0; end
else begin state<=s1;vout<=0; end
end
s2: begin
if(vin==0) begin state<=s0;vout<=0; end
else begin state<=s1;vout<=1; end
end
default:state<=s0;
endcase
end
endmodule