Setting log file to 'F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/I2S_Controller.v
(VERI-1482) Analyzing Verilog file F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/i2s_rx.v
(VERI-1482) Analyzing Verilog file F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/i2s_tx.v
(VERI-1482) Analyzing Verilog file F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/testbench/Verilog/I2S_Controller_tb.v
INFO - F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/testbench/Verilog/I2S_Controller_tb.v(56,14-56,26) (VERI-1328) analyzing included file F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/testbench/Verilog/testcase.v
INFO - F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/testbench/Verilog/testcase.v(7,10-7,19) (VERI-1328) analyzing included file F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/testbench/Verilog/tasks.v
INFO - F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/testbench/Verilog/I2S_Controller_tb.v(11,8-11,25) (VERI-1018) compiling module I2S_Controller_tb
INFO - F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/testbench/Verilog/I2S_Controller_tb.v(11,1-129,14) (VERI-9000) elaborating module 'I2S_Controller_tb'
INFO - F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/I2S_Controller.v(18,1-101,10) (VERI-9000) elaborating module 'I2S_Controller_uniq_1'
INFO - F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/testbench/Verilog/I2S_Controller_tb.v(11,1-129,14) (VERI-9000) elaborating module 'I2S_Controller_tb'
INFO - F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/I2S_Controller.v(18,1-101,10) (VERI-9000) elaborating module 'I2S_Controller_uniq_1'
INFO - F:/FPFA_Audio/projects/I2Scontroller/PROJECT_I2S_CONTROLLER/i2s_tx.v(11,1-183,10) (VERI-9000) elaborating module 'i2s_tx_uniq_1'
Done: design load finished with (0) errors, and (0) warnings