Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.7.0.96.1

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Wed Nov 09 17:22:52 2016


Command Line:  synthesis -f Picture_display_impl1_lattice.synproj -gui -msgset F:/Picture_display/promote.xml 

Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is CSBGA132.
The -d option is LCMXO2-4000HC.
Using package CSBGA132.
Using performance grade 4.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-4000HC

### Package : CSBGA132

### Speed   : 4

##########################################################

                                                          

Optimization goal = Balanced
Top-level module name = Picture_display.
Target frequency = 1.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p F:/Picture_display (searchpath added)
-p C:/lscc/diamond/3.7_x64/ispfpga/xo2c00/data (searchpath added)
-p F:/Picture_display/impl1 (searchpath added)
-p F:/Picture_display (searchpath added)
Verilog design file = F:/Picture_display/Picture_display.v
Verilog design file = F:/Picture_display/LCD_RGB.v
Verilog design file = F:/Picture_display/LCD_RAM.v
NGD file = Picture_display_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file f:/picture_display/picture_display.v. VERI-1482
Analyzing Verilog file f:/picture_display/lcd_rgb.v. VERI-1482
Analyzing Verilog file f:/picture_display/lcd_ram.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): Picture_display
INFO - synthesis: f:/picture_display/picture_display.v(18): compiling module Picture_display. VERI-1018
INFO - synthesis: f:/picture_display/lcd_rgb.v(18): compiling module LCD_RGB. VERI-1018
WARNING - synthesis: f:/picture_display/lcd_rgb.v(224): expression size 33 truncated to fit in target size 9. VERI-1209
WARNING - synthesis: f:/picture_display/lcd_rgb.v(229): expression size 33 truncated to fit in target size 9. VERI-1209
WARNING - synthesis: f:/picture_display/lcd_rgb.v(67): net reg_setxy does not have a driver. VDB-1002
WARNING - synthesis: f:/picture_display/lcd_rgb.v(68): net reg_init does not have a driver. VDB-1002
WARNING - synthesis: f:/picture_display/picture_display.v(40): actual bit length 133 differs from formal bit length 132 for port ram_lcd_data. VERI-1330
INFO - synthesis: f:/picture_display/lcd_ram.v(8): compiling module LCD_RAM. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_1. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_2. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_3. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_4. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_5. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_6. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_7. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120): compiling module VHI. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124): compiling module VLO. VERI-1018
INFO - synthesis: C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC(CSDECODE_B="0b111",RESETMODE="ASYNC"). VERI-1018
WARNING - synthesis: f:/picture_display/picture_display.v(57): actual bit length 133 differs from formal bit length 132 for port Q. VERI-1330
Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.7_x64/ispfpga.
Package Status:                     Final          Version 1.3.
Top-level module name = Picture_display.
WARNING - synthesis: f:/picture_display/lcd_rgb.v(67): ram reg_setxy_original_ramnet has no write-port on it. VDB-1038
WARNING - synthesis: f:/picture_display/lcd_rgb.v(68): ram reg_init_original_ramnet has no write-port on it. VDB-1038



WARNING - synthesis: f:/picture_display/lcd_rgb.v(214): Register \LCD_RGB_uut/num_delay_i0 is stuck at Zero. VDB-5013
WARNING - synthesis: f:/picture_display/lcd_rgb.v(214): Register \LCD_RGB_uut/num_delay_i4 is stuck at One. VDB-5014
GSR instance connected to net rst_n_in_c.
Duplicate register/latch removal. \LCD_RGB_uut/num_delay_i3 is a one-to-one match with \LCD_RGB_uut/num_delay_i7.
Duplicate register/latch removal. \LCD_RGB_uut/num_delay_i8 is a one-to-one match with \LCD_RGB_uut/num_delay_i9.
Duplicate register/latch removal. \LCD_RGB_uut/num_delay_i14 is a one-to-one match with \LCD_RGB_uut/num_delay_i15.
Applying 1.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in Picture_display_drc.log.
Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.7_x64/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file Picture_display_impl1.ngd.

################### Begin Area Report (Picture_display)######################
Number of register bits => 231 of 4635 (4 % )
CCU2D => 37
DP8KC => 8
FD1P3AX => 204
FD1P3IX => 24
FD1P3JX => 3
GSR => 1
IB => 2
L6MUX21 => 26
LUT4 => 339
OB => 5
PFUMX => 54
ROM128X1A => 7
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 1
  Net : clk_in_c, loads : 246
Clock Enable Nets
Number of Clock Enables: 31
Top 10 highest fanout Clock Enables:
  Net : LCD_RGB_uut/clk_in_c_enable_179, loads : 50
  Net : LCD_RGB_uut/clk_in_c_enable_129, loads : 50
  Net : LCD_RGB_uut/clk_in_c_enable_211, loads : 32
  Net : LCD_RGB_uut/clk_in_c_enable_39, loads : 16
  Net : LCD_RGB_uut/clk_in_c_enable_51, loads : 13
  Net : LCD_RGB_uut/clk_in_c_enable_224, loads : 9
  Net : LCD_RGB_uut/clk_in_c_enable_231, loads : 8
  Net : LCD_RGB_uut/clk_in_c_enable_230, loads : 8
  Net : LCD_RGB_uut/clk_in_c_enable_226, loads : 6
  Net : LCD_RGB_uut/clk_in_c_enable_65, loads : 5
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : LCD_RGB_uut/state_0, loads : 71
  Net : LCD_RGB_uut/x_cnt_0, loads : 67
  Net : LCD_RGB_uut/state_1, loads : 64
  Net : LCD_RGB_uut/state_2, loads : 50
  Net : LCD_RGB_uut/clk_in_c_enable_129, loads : 50
  Net : LCD_RGB_uut/clk_in_c_enable_179, loads : 50
  Net : LCD_RGB_uut/x_cnt_1, loads : 34
  Net : LCD_RGB_uut/clk_in_c_enable_211, loads : 32
  Net : LCD_RGB_uut/cnt_scan_2, loads : 30
  Net : LCD_RGB_uut/ram_clk_en, loads : 29
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 1000.000000 -name  |             |             |
clk0 [get_nets clk_in_c]                |    1.000 MHz|   64.658 MHz|    10  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 70.355  MB

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Elapsed CPU time for LSE flow : 5.141  secs
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