Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Wed Nov 09 17:22:56 2016 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: Picture_display Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 1000.000000 -name clk0 [get_nets clk_in_c] 1062 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 984.534ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \LCD_RGB_uut/cnt_i7 (from clk_in_c +) Destination: FD1P3AX SP \LCD_RGB_uut/state_i1 (to clk_in_c +) Delay: 15.181ns (30.4% logic, 69.6% route), 10 logic levels. Constraint Details: 15.181ns data_path \LCD_RGB_uut/cnt_i7 to \LCD_RGB_uut/state_i1 meets 1000.000ns delay constraint less 0.285ns LCE_S requirement (totaling 999.715ns) by 984.534ns Path Details: \LCD_RGB_uut/cnt_i7 to \LCD_RGB_uut/state_i1 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \LCD_RGB_uut/cnt_i7 (from clk_in_c) Route 2 e 1.198 \LCD_RGB_uut/cnt[7] LUT4 --- 0.493 D to Z \LCD_RGB_uut/i6_4_lut Route 1 e 0.941 \LCD_RGB_uut/n15 LUT4 --- 0.493 A to Z \LCD_RGB_uut/i8_4_lut Route 2 e 1.141 \LCD_RGB_uut/n6228 LUT4 --- 0.493 D to Z \LCD_RGB_uut/i2_3_lut_4_lut_adj_17 Route 3 e 1.258 \LCD_RGB_uut/n9982 LUT4 --- 0.493 B to Z \LCD_RGB_uut/i1_4_lut_adj_3 Route 9 e 1.574 \LCD_RGB_uut/n211 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i1_2_lut_rep_92_3_lut Route 5 e 1.405 \LCD_RGB_uut/n10610 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i1_2_lut_3_lut_3_lut_4_lut Route 2 e 1.141 \LCD_RGB_uut/n7467 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i1_4_lut_adj_71 Route 1 e 0.020 \LCD_RGB_uut/n35_adj_580 MUXL5 --- 0.233 ALUT to Z \LCD_RGB_uut/i33 Route 1 e 0.941 \LCD_RGB_uut/n9724 LUT4 --- 0.493 B to Z \LCD_RGB_uut/i58_4_lut Route 1 e 0.941 \LCD_RGB_uut/clk_in_c_enable_70 -------- 15.181 (30.4% logic, 69.6% route), 10 logic levels. Passed: The following path meets requirements by 984.534ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \LCD_RGB_uut/cnt_i7 (from clk_in_c +) Destination: FD1P3AX SP \LCD_RGB_uut/state_i0 (to clk_in_c +) Delay: 15.181ns (30.4% logic, 69.6% route), 10 logic levels. Constraint Details: 15.181ns data_path \LCD_RGB_uut/cnt_i7 to \LCD_RGB_uut/state_i0 meets 1000.000ns delay constraint less 0.285ns LCE_S requirement (totaling 999.715ns) by 984.534ns Path Details: \LCD_RGB_uut/cnt_i7 to \LCD_RGB_uut/state_i0 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \LCD_RGB_uut/cnt_i7 (from clk_in_c) Route 2 e 1.198 \LCD_RGB_uut/cnt[7] LUT4 --- 0.493 D to Z \LCD_RGB_uut/i6_4_lut Route 1 e 0.941 \LCD_RGB_uut/n15 LUT4 --- 0.493 A to Z \LCD_RGB_uut/i8_4_lut Route 2 e 1.141 \LCD_RGB_uut/n6228 LUT4 --- 0.493 D to Z \LCD_RGB_uut/i2_3_lut_4_lut_adj_17 Route 3 e 1.258 \LCD_RGB_uut/n9982 LUT4 --- 0.493 B to Z \LCD_RGB_uut/i1_4_lut_adj_3 Route 9 e 1.574 \LCD_RGB_uut/n211 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i1_2_lut_rep_92_3_lut Route 5 e 1.405 \LCD_RGB_uut/n10610 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i1_2_lut_3_lut_3_lut_4_lut Route 2 e 1.141 \LCD_RGB_uut/n7467 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i1_4_lut_adj_64 Route 1 e 0.020 \LCD_RGB_uut/n23_adj_579 MUXL5 --- 0.233 ALUT to Z \LCD_RGB_uut/i40 Route 1 e 0.941 \LCD_RGB_uut/n17 LUT4 --- 0.493 A to Z \LCD_RGB_uut/i38_4_lut Route 1 e 0.941 \LCD_RGB_uut/clk_in_c_enable_225 -------- 15.181 (30.4% logic, 69.6% route), 10 logic levels. Passed: The following path meets requirements by 984.534ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3AX CK \LCD_RGB_uut/cnt_i8 (from clk_in_c +) Destination: FD1P3AX SP \LCD_RGB_uut/state_i1 (to clk_in_c +) Delay: 15.181ns (30.4% logic, 69.6% route), 10 logic levels. Constraint Details: 15.181ns data_path \LCD_RGB_uut/cnt_i8 to \LCD_RGB_uut/state_i1 meets 1000.000ns delay constraint less 0.285ns LCE_S requirement (totaling 999.715ns) by 984.534ns Path Details: \LCD_RGB_uut/cnt_i8 to \LCD_RGB_uut/state_i1 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.444 CK to Q \LCD_RGB_uut/cnt_i8 (from clk_in_c) Route 2 e 1.198 \LCD_RGB_uut/cnt[8] LUT4 --- 0.493 A to Z \LCD_RGB_uut/i5_3_lut Route 1 e 0.941 \LCD_RGB_uut/n14 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i8_4_lut Route 2 e 1.141 \LCD_RGB_uut/n6228 LUT4 --- 0.493 D to Z \LCD_RGB_uut/i2_3_lut_4_lut_adj_17 Route 3 e 1.258 \LCD_RGB_uut/n9982 LUT4 --- 0.493 B to Z \LCD_RGB_uut/i1_4_lut_adj_3 Route 9 e 1.574 \LCD_RGB_uut/n211 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i1_2_lut_rep_92_3_lut Route 5 e 1.405 \LCD_RGB_uut/n10610 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i1_2_lut_3_lut_3_lut_4_lut Route 2 e 1.141 \LCD_RGB_uut/n7467 LUT4 --- 0.493 C to Z \LCD_RGB_uut/i1_4_lut_adj_71 Route 1 e 0.020 \LCD_RGB_uut/n35_adj_580 MUXL5 --- 0.233 ALUT to Z \LCD_RGB_uut/i33 Route 1 e 0.941 \LCD_RGB_uut/n9724 LUT4 --- 0.493 B to Z \LCD_RGB_uut/i58_4_lut Route 1 e 0.941 \LCD_RGB_uut/clk_in_c_enable_70 -------- 15.181 (30.4% logic, 69.6% route), 10 logic levels. Report: 15.466 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets clk_in_c] | 1000.000 ns| 15.466 ns| 10 | | | -------------------------------------------------------------------------------- All constraints were met. Timing summary: --------------- Timing errors: 0 Score: 0 Constraints cover 7579 paths, 864 nets, and 2362 connections (98.7% coverage) Peak memory: 73699328 bytes, TRCE: 1196032 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs