Lattice Mapping Report File for Design Module 'Picture_display' Design Information Command line: map -a MachXO2 -p LCMXO2-4000HC -t CSBGA132 -s 4 -oc Commercial Picture_display_impl1.ngd -o Picture_display_impl1_map.ncd -pr Picture_display_impl1.prf -mp Picture_display_impl1.mrp -lpf F:/Picture_display/impl1/Picture_display_impl1.lpf -lpf F:/Picture_display/Picture_display.lpf -c 0 -gui -msgset F:/Picture_display/promote.xml Target Vendor: LATTICE Target Device: LCMXO2-4000HCCSBGA132 Target Performance: 4 Mapper: xo2c00, version: Diamond (64-bit) 3.7.0.96.1 Mapped on: 11/09/16 17:22:57 Design Summary Number of registers: 231 out of 4635 (5%) PFU registers: 231 out of 4320 (5%) PIO registers: 0 out of 315 (0%) Number of SLICEs: 237 out of 2160 (11%) SLICEs as Logic/ROM: 237 out of 2160 (11%) SLICEs as RAM: 0 out of 1620 (0%) SLICEs as Carry: 37 out of 2160 (2%) Number of LUT4s: 471 out of 4320 (11%) Number used as logic LUTs: 397 Number used as distributed RAM: 0 Number used as ripple logic: 74 Number used as shift registers: 0 Number of PIO sites used: 7 + 4(JTAG) out of 105 (10%) Number of block RAMs: 8 out of 10 (80%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 2 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 1 Net clk_in_c: 145 loads, 145 rising, 0 falling (Driver: PIO clk_in ) Number of Clock Enables: 31 Net LCD_RGB_uut/clk_in_c_enable_60: 2 loads, 2 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_78: 2 loads, 2 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_39: 8 loads, 8 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_51: 7 loads, 7 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_4: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_5: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_55: 2 loads, 2 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_7: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_70: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_228: 2 loads, 2 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_227: 2 loads, 2 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_129: 25 loads, 25 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_231: 4 loads, 4 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_65: 4 loads, 4 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_18: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_57: 2 loads, 2 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_226: 4 loads, 4 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_224: 6 loads, 6 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_17: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_71: 2 loads, 2 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_211: 16 loads, 16 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_67: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_220: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_69: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_230: 4 loads, 4 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_221: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_222: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_225: 1 loads, 1 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_179: 25 loads, 25 LSLICEs Net LCD_RGB_uut/clk_in_c_enable_229: 1 loads, 1 LSLICEs Net ram_clk_en: 30 loads, 0 LSLICEs Number of LSRs: 6 Net rst_n_in_c: 15 loads, 0 LSLICEs Net LCD_RGB_uut/n7102: 2 loads, 2 LSLICEs Net LCD_RGB_uut/n7104: 2 loads, 2 LSLICEs Net LCD_RGB_uut/n9562: 2 loads, 2 LSLICEs Net LCD_RGB_uut/n7110: 3 loads, 3 LSLICEs Net LCD_RGB_uut/n7096: 8 loads, 8 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net state_0: 72 loads Net LCD_RGB_uut/x_cnt_0: 67 loads Net LCD_RGB_uut/state_1: 64 loads Net cnt_3: 60 loads Net cnt_1: 56 loads Net cnt_2: 52 loads Net cnt_5: 51 loads Net LCD_RGB_uut/state_2: 50 loads Net cnt_6: 37 loads Net LCD_RGB_uut/x_cnt_1: 34 loads Number of warnings: 0 Number of errors: 0 Design Errors/Warnings No errors or warnings present. IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | lcd_rst_n_out | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | lcd_bl_out | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | lcd_dc_out | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | lcd_clk_out | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | lcd_data_out | OUTPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | clk_in | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ | rst_n_in | INPUT | LVCMOS33 | | +---------------------+-----------+-----------+------------+ Removed logic Signal n10645 was merged into signal rst_n_in_c Signal GND_net undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_52_1/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_52_1/CI undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_116_17/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_116_17/CO undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_447_1/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_447_1/CI undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_52_9/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_52_9/CO undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_447_9/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_447_9/CO undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_116_1/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_116_1/CI undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_39_1/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_39_1/CI undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_2/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_2/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_2/CI undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_4/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_4/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_6/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_6/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_8/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_8/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_10/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_10/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_12/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_12/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_14/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_14/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_16/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_16/S0 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_cout/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/sub_590_add_2_cout/CO undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_39_17/S1 undriven or does not drive anything - clipped. Signal LCD_RGB_uut/add_39_17/CO undriven or does not drive anything - clipped. Block rst_n_in_I_0_1_lut_rep_127 was optimized away. Block i1 was optimized away. Memory Usage INFO: Design contains EBR with GSR enabled. The GSR is only applicable for output registers except FIFO. /ram_data_131__I_0: EBRs: 8 RAM SLICEs: 0 Logic SLICEs: 0 PFU Registers: 0 -Contains EBR LCD_RAM_0_7_0: TYPE= DP8KC, Width_A= 6, Depth_A= 256, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= ENABLED, MEM_INIT_FILE= 128x160.mem, MEM_LPC_FILE= LCD_RAM.lpc -Contains EBR LCD_RAM_0_1_6: TYPE= DP8KC, Width_A= 9, Width_B= 9, Depth_A= 256, Depth_B= 256, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= ENABLED, MEM_INIT_FILE= 128x160.mem, MEM_LPC_FILE= LCD_RAM.lpc -Contains EBR LCD_RAM_0_0_7: TYPE= DP8KC, Width_A= 9, Width_B= 9, Depth_A= 256, Depth_B= 256, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= ENABLED, MEM_INIT_FILE= 128x160.mem, MEM_LPC_FILE= LCD_RAM.lpc -Contains EBR LCD_RAM_0_2_5: TYPE= DP8KC, Width_A= 9, Width_B= 9, Depth_A= 256, Depth_B= 256, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= ENABLED, MEM_INIT_FILE= 128x160.mem, MEM_LPC_FILE= LCD_RAM.lpc -Contains EBR LCD_RAM_0_3_4: TYPE= DP8KC, Width_A= 9, Width_B= 9, Depth_A= 256, Depth_B= 256, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= ENABLED, MEM_INIT_FILE= 128x160.mem, MEM_LPC_FILE= LCD_RAM.lpc -Contains EBR LCD_RAM_0_4_3: TYPE= DP8KC, Width_A= 9, Width_B= 9, Depth_A= 256, Depth_B= 256, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= ENABLED, MEM_INIT_FILE= 128x160.mem, MEM_LPC_FILE= LCD_RAM.lpc -Contains EBR LCD_RAM_0_5_2: TYPE= DP8KC, Width_A= 9, Width_B= 9, Depth_A= 256, Depth_B= 256, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= ENABLED, MEM_INIT_FILE= 128x160.mem, MEM_LPC_FILE= LCD_RAM.lpc -Contains EBR LCD_RAM_0_6_1: TYPE= DP8KC, Width_A= 9, Width_B= 9, Depth_A= 256, Depth_B= 256, REGMODE_A= NOREG, REGMODE_B= NOREG, RESETMODE= ASYNC, ASYNC_RESET_RELEASE= SYNC, WRITEMODE_A= NORMAL, WRITEMODE_B= NORMAL, GSR= ENABLED, MEM_INIT_FILE= 128x160.mem, MEM_LPC_FILE= LCD_RAM.lpc ASIC Components --------------- Instance Name: ram_data_131__I_0/LCD_RAM_0_7_0 Type: DP8KC Instance Name: ram_data_131__I_0/LCD_RAM_0_1_6 Type: DP8KC Instance Name: ram_data_131__I_0/LCD_RAM_0_0_7 Type: DP8KC Instance Name: ram_data_131__I_0/LCD_RAM_0_2_5 Type: DP8KC Instance Name: ram_data_131__I_0/LCD_RAM_0_3_4 Type: DP8KC Instance Name: ram_data_131__I_0/LCD_RAM_0_4_3 Type: DP8KC Instance Name: ram_data_131__I_0/LCD_RAM_0_5_2 Type: DP8KC Instance Name: ram_data_131__I_0/LCD_RAM_0_6_1 Type: DP8KC GSR Usage --------- GSR Component: The Global Set Reset (GSR) resource has been used to implement a global reset of the design. The reset signal used for GSR control is 'rst_n_in_c'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Components with disabled GSR Property ------------------------------------- These components have the GSR property set to DISABLED. The components will not respond to the reset signal 'rst_n_in_c' via the GSR component. Type and number of components of the type: Register = 145 Type and instance name of component: Register : LCD_RGB_uut/data_reg_i0_i0 Register : LCD_RGB_uut/lcd_dc_out_184 Register : LCD_RGB_uut/ram_data_r_i0_i0 Register : LCD_RGB_uut/data_reg_i0_i8 Register : LCD_RGB_uut/data_reg_i0_i1 Register : LCD_RGB_uut/data_reg_i0_i2 Register : LCD_RGB_uut/data_reg_i0_i3 Register : LCD_RGB_uut/data_reg_i0_i4 Register : LCD_RGB_uut/data_reg_i0_i5 Register : LCD_RGB_uut/data_reg_i0_i6 Register : LCD_RGB_uut/data_reg_i0_i7 Register : LCD_RGB_uut/ram_data_r_i0_i1 Register : LCD_RGB_uut/ram_data_r_i0_i2 Register : LCD_RGB_uut/ram_data_r_i0_i3 Register : LCD_RGB_uut/ram_data_r_i0_i4 Register : LCD_RGB_uut/ram_data_r_i0_i5 Register : LCD_RGB_uut/ram_data_r_i0_i6 Register : LCD_RGB_uut/ram_data_r_i0_i7 Register : LCD_RGB_uut/ram_data_r_i0_i8 Register : LCD_RGB_uut/ram_data_r_i0_i9 Register : LCD_RGB_uut/ram_data_r_i0_i10 Register : LCD_RGB_uut/ram_data_r_i0_i11 Register : LCD_RGB_uut/ram_data_r_i0_i12 Register : LCD_RGB_uut/ram_data_r_i0_i13 Register : LCD_RGB_uut/ram_data_r_i0_i14 Register : LCD_RGB_uut/ram_data_r_i0_i15 Register : LCD_RGB_uut/ram_data_r_i0_i16 Register : LCD_RGB_uut/ram_data_r_i0_i17 Register : LCD_RGB_uut/ram_data_r_i0_i18 Register : LCD_RGB_uut/ram_data_r_i0_i19 Register : LCD_RGB_uut/ram_data_r_i0_i20 Register : LCD_RGB_uut/ram_data_r_i0_i21 Register : LCD_RGB_uut/ram_data_r_i0_i22 Register : LCD_RGB_uut/ram_data_r_i0_i23 Register : LCD_RGB_uut/ram_data_r_i0_i24 Register : LCD_RGB_uut/ram_data_r_i0_i25 Register : LCD_RGB_uut/ram_data_r_i0_i26 Register : LCD_RGB_uut/ram_data_r_i0_i27 Register : LCD_RGB_uut/ram_data_r_i0_i28 Register : LCD_RGB_uut/ram_data_r_i0_i29 Register : LCD_RGB_uut/ram_data_r_i0_i30 Register : LCD_RGB_uut/ram_data_r_i0_i31 Register : LCD_RGB_uut/ram_data_r_i0_i32 Register : LCD_RGB_uut/ram_data_r_i0_i33 Register : LCD_RGB_uut/ram_data_r_i0_i34 Register : LCD_RGB_uut/ram_data_r_i0_i35 Register : LCD_RGB_uut/ram_data_r_i0_i36 Register : LCD_RGB_uut/ram_data_r_i0_i37 Register : LCD_RGB_uut/ram_data_r_i0_i38 Register : LCD_RGB_uut/ram_data_r_i0_i39 Register : LCD_RGB_uut/ram_data_r_i0_i40 Register : LCD_RGB_uut/ram_data_r_i0_i41 Register : LCD_RGB_uut/ram_data_r_i0_i42 Register : LCD_RGB_uut/ram_data_r_i0_i43 Register : LCD_RGB_uut/ram_data_r_i0_i44 Register : LCD_RGB_uut/ram_data_r_i0_i45 Register : LCD_RGB_uut/ram_data_r_i0_i46 Register : LCD_RGB_uut/ram_data_r_i0_i47 Register : LCD_RGB_uut/ram_data_r_i0_i48 Register : LCD_RGB_uut/ram_data_r_i0_i49 Register : LCD_RGB_uut/ram_data_r_i0_i50 Register : LCD_RGB_uut/ram_data_r_i0_i51 Register : LCD_RGB_uut/ram_data_r_i0_i52 Register : LCD_RGB_uut/ram_data_r_i0_i53 Register : LCD_RGB_uut/ram_data_r_i0_i54 Register : LCD_RGB_uut/ram_data_r_i0_i55 Register : LCD_RGB_uut/ram_data_r_i0_i56 Register : LCD_RGB_uut/ram_data_r_i0_i57 Register : LCD_RGB_uut/ram_data_r_i0_i58 Register : LCD_RGB_uut/ram_data_r_i0_i59 Register : LCD_RGB_uut/ram_data_r_i0_i60 Register : LCD_RGB_uut/ram_data_r_i0_i61 Register : LCD_RGB_uut/ram_data_r_i0_i62 Register : LCD_RGB_uut/ram_data_r_i0_i63 Register : LCD_RGB_uut/ram_data_r_i0_i64 Register : LCD_RGB_uut/ram_data_r_i0_i65 Register : LCD_RGB_uut/ram_data_r_i0_i66 Register : LCD_RGB_uut/ram_data_r_i0_i67 Register : LCD_RGB_uut/ram_data_r_i0_i68 Register : LCD_RGB_uut/ram_data_r_i0_i69 Register : LCD_RGB_uut/ram_data_r_i0_i70 Register : LCD_RGB_uut/ram_data_r_i0_i71 Register : LCD_RGB_uut/ram_data_r_i0_i72 Register : LCD_RGB_uut/ram_data_r_i0_i73 Register : LCD_RGB_uut/ram_data_r_i0_i74 Register : LCD_RGB_uut/ram_data_r_i0_i75 Register : LCD_RGB_uut/ram_data_r_i0_i76 Register : LCD_RGB_uut/ram_data_r_i0_i77 Register : LCD_RGB_uut/ram_data_r_i0_i78 Register : LCD_RGB_uut/ram_data_r_i0_i79 Register : LCD_RGB_uut/ram_data_r_i0_i80 Register : LCD_RGB_uut/ram_data_r_i0_i81 Register : LCD_RGB_uut/ram_data_r_i0_i82 Register : LCD_RGB_uut/ram_data_r_i0_i83 Register : LCD_RGB_uut/ram_data_r_i0_i84 Register : LCD_RGB_uut/ram_data_r_i0_i85 Register : LCD_RGB_uut/ram_data_r_i0_i86 Register : LCD_RGB_uut/ram_data_r_i0_i87 Register : LCD_RGB_uut/ram_data_r_i0_i88 Register : LCD_RGB_uut/ram_data_r_i0_i89 Register : LCD_RGB_uut/ram_data_r_i0_i90 Register : LCD_RGB_uut/ram_data_r_i0_i91 Register : LCD_RGB_uut/ram_data_r_i0_i92 Register : LCD_RGB_uut/ram_data_r_i0_i93 Register : LCD_RGB_uut/ram_data_r_i0_i94 Register : LCD_RGB_uut/ram_data_r_i0_i95 Register : LCD_RGB_uut/ram_data_r_i0_i96 Register : LCD_RGB_uut/ram_data_r_i0_i97 Register : LCD_RGB_uut/ram_data_r_i0_i98 Register : LCD_RGB_uut/ram_data_r_i0_i99 Register : LCD_RGB_uut/ram_data_r_i0_i100 Register : LCD_RGB_uut/ram_data_r_i0_i101 Register : LCD_RGB_uut/ram_data_r_i0_i102 Register : LCD_RGB_uut/ram_data_r_i0_i103 Register : LCD_RGB_uut/ram_data_r_i0_i104 Register : LCD_RGB_uut/ram_data_r_i0_i105 Register : LCD_RGB_uut/ram_data_r_i0_i106 Register : LCD_RGB_uut/ram_data_r_i0_i107 Register : LCD_RGB_uut/ram_data_r_i0_i108 Register : LCD_RGB_uut/ram_data_r_i0_i109 Register : LCD_RGB_uut/ram_data_r_i0_i110 Register : LCD_RGB_uut/ram_data_r_i0_i111 Register : LCD_RGB_uut/ram_data_r_i0_i112 Register : LCD_RGB_uut/ram_data_r_i0_i113 Register : LCD_RGB_uut/ram_data_r_i0_i114 Register : LCD_RGB_uut/ram_data_r_i0_i115 Register : LCD_RGB_uut/ram_data_r_i0_i116 Register : LCD_RGB_uut/ram_data_r_i0_i117 Register : LCD_RGB_uut/ram_data_r_i0_i118 Register : LCD_RGB_uut/ram_data_r_i0_i119 Register : LCD_RGB_uut/ram_data_r_i0_i120 Register : LCD_RGB_uut/ram_data_r_i0_i121 Register : LCD_RGB_uut/ram_data_r_i0_i122 Register : LCD_RGB_uut/ram_data_r_i0_i123 Register : LCD_RGB_uut/ram_data_r_i0_i124 Register : LCD_RGB_uut/ram_data_r_i0_i125 Register : LCD_RGB_uut/ram_data_r_i0_i126 Register : LCD_RGB_uut/ram_data_r_i0_i127 Register : LCD_RGB_uut/ram_data_r_i0_i128 Register : LCD_RGB_uut/ram_data_r_i0_i129 Register : LCD_RGB_uut/ram_data_r_i0_i130 Register : LCD_RGB_uut/ram_data_r_i0_i131 Register : LCD_RGB_uut/lcd_rst_n_out_189 Register : LCD_RGB_uut/lcd_data_out_186 Register : LCD_RGB_uut/lcd_clk_out_185 Components with synchronous local reset also reset by asynchronous GSR ---------------------------------------------------------------------- These components have the GSR property set to ENABLED and the local reset is synchronous. The components will respond to the synchronous local reset and to the unrelated asynchronous reset signal 'rst_n_in_c' via the GSR component. Type and number of components of the type: Register = 27 Type and instance name of component: Register : LCD_RGB_uut/num_delay_i5 Register : LCD_RGB_uut/num_delay_i1 Register : LCD_RGB_uut/x_cnt_i4 Register : LCD_RGB_uut/x_cnt_i3 Register : LCD_RGB_uut/x_cnt_i2 Register : LCD_RGB_uut/x_cnt_i1 Register : LCD_RGB_uut/cnt_write_i5 Register : LCD_RGB_uut/cnt_write_i4 Register : LCD_RGB_uut/cnt_write_i3 Register : LCD_RGB_uut/cnt_write_i2 Register : LCD_RGB_uut/cnt_write_i1 Register : LCD_RGB_uut/cnt_init_i2 Register : LCD_RGB_uut/cnt_init_i1 Register : LCD_RGB_uut/cnt_main_i2 Register : LCD_RGB_uut/cnt_main_i1 Register : LCD_RGB_uut/ram_lcd_addr_i7 Register : LCD_RGB_uut/ram_lcd_addr_i6 Register : LCD_RGB_uut/ram_lcd_addr_i5 Register : LCD_RGB_uut/ram_lcd_addr_i4 Register : LCD_RGB_uut/ram_lcd_addr_i3 Register : LCD_RGB_uut/ram_lcd_addr_i2 Register : LCD_RGB_uut/ram_lcd_addr_i1 Register : LCD_RGB_uut/x_cnt_i0 Register : LCD_RGB_uut/high_word_180 Register : LCD_RGB_uut/cnt_init_i0 Register : LCD_RGB_uut/cnt_main_i0 Register : LCD_RGB_uut/ram_lcd_addr_i0 EBR components with enabled GSR ------------------------------- These EBR components have the GSR property set to ENABLED. The components will respond to the asynchronous reset signal 'rst_n_in_c' via the GSR component. Type and number of components of the type: DP8KC = 8 Type and instance name of component: DP8KC : ram_data_131__I_0/LCD_RAM_0_7_0 DP8KC : ram_data_131__I_0/LCD_RAM_0_1_6 DP8KC : ram_data_131__I_0/LCD_RAM_0_0_7 DP8KC : ram_data_131__I_0/LCD_RAM_0_2_5 DP8KC : ram_data_131__I_0/LCD_RAM_0_3_4 DP8KC : ram_data_131__I_0/LCD_RAM_0_4_3 DP8KC : ram_data_131__I_0/LCD_RAM_0_5_2 DP8KC : ram_data_131__I_0/LCD_RAM_0_6_1 Run Time and Memory Usage ------------------------- Total CPU Time: 1 secs Total REAL Time: 0 secs Peak Memory Usage: 52 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.