PAR: Place And Route Diamond (64-bit) 3.7.0.96.1. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved. Wed Nov 09 17:23:01 2016 C:/lscc/diamond/3.7_x64/ispfpga\bin\nt64\par -f Picture_display_impl1.p2t Picture_display_impl1_map.ncd Picture_display_impl1.dir Picture_display_impl1.prf -gui -msgset F:/Picture_display/promote.xml Preference file: Picture_display_impl1.prf. Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 - - - - 12 Complete * : Design saved. Total (real) run time for 1-seed: 12 secs par done! Lattice Place and Route Report for Design "Picture_display_impl1_map.ncd" Wed Nov 09 17:23:01 2016 Best Par Run PAR: Place And Route Diamond (64-bit) 3.7.0.96.1. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset F:/Picture_display/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF Picture_display_impl1_map.ncd Picture_display_impl1.dir/5_1.ncd Picture_display_impl1.prf Preference file: Picture_display_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file Picture_display_impl1_map.ncd. Design name: Picture_display NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-4000HC Package: CSBGA132 Performance: 4 Loading device for application par from file 'xo2c4000.nph' in environment: C:/lscc/diamond/3.7_x64/ispfpga. Package Status: Final Version 1.3. Performance Hardware Data Status: Final Version 33.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 7+4(JTAG)/280 4% used 7+4(JTAG)/105 10% bonded SLICE 237/2160 10% used GSR 1/1 100% used EBR 8/10 80% used INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details. Number of Signals: 810 Number of Connections: 2300 Pin Constraint Summary: 7 out of 7 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: clk_in_c (driver: clk_in, clk load #: 145) WARNING - par: Signal "clk_in_c" is selected to use Primary clock resources. However, its driver comp "clk_in" is located at "C1", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. The following 5 signals are selected to use the secondary clock routing resources: ram_clk_en (driver: LCD_RGB_uut/SLICE_162, clk load #: 0, sr load #: 0, ce load #: 30) LCD_RGB_uut/clk_in_c_enable_129 (driver: LCD_RGB_uut/SLICE_269, clk load #: 0, sr load #: 0, ce load #: 25) LCD_RGB_uut/clk_in_c_enable_179 (driver: LCD_RGB_uut/SLICE_261, clk load #: 0, sr load #: 0, ce load #: 25) LCD_RGB_uut/clk_in_c_enable_211 (driver: LCD_RGB_uut/SLICE_296, clk load #: 0, sr load #: 0, ce load #: 16) rst_n_in_c (driver: rst_n_in, clk load #: 0, sr load #: 15, ce load #: 0) WARNING - par: Signal "rst_n_in_c" is selected to use Secondary clock resources. However, its driver comp "rst_n_in" is located at "L14", which is not a dedicated pin for connecting to Secondary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew. Signal rst_n_in_c is selected as Global Set/Reset. Starting Placer Phase 0. ............ Finished Placer Phase 0. REAL time: 2 secs Starting Placer Phase 1. .................... Placer score = 131141. Finished Placer Phase 1. REAL time: 7 secs Starting Placer Phase 2. . Placer score = 130871 Finished Placer Phase 2. REAL time: 7 secs Clock Report Global Clock Resources: CLK_PIN : 0 out of 8 (0%) General PIO: 2 out of 280 (0%) PLL : 0 out of 2 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Quadrants All (TL, TR, BL, BR) - Global Clocks: PRIMARY "clk_in_c" from comp "clk_in" on PIO site "C1 (PL4A)", clk load = 145 SECONDARY "ram_clk_en" from Q0 on comp "LCD_RGB_uut/SLICE_162" on site "R12C17B", clk load = 0, ce load = 30, sr load = 0 SECONDARY "LCD_RGB_uut/clk_in_c_enable_129" from F0 on comp "LCD_RGB_uut/SLICE_269" on site "R12C15A", clk load = 0, ce load = 25, sr load = 0 SECONDARY "LCD_RGB_uut/clk_in_c_enable_179" from F1 on comp "LCD_RGB_uut/SLICE_261" on site "R12C15C", clk load = 0, ce load = 25, sr load = 0 SECONDARY "LCD_RGB_uut/clk_in_c_enable_211" from F0 on comp "LCD_RGB_uut/SLICE_296" on site "R12C15D", clk load = 0, ce load = 16, sr load = 0 SECONDARY "rst_n_in_c" from comp "rst_n_in" on PIO site "L14 (PR16A)", clk load = 0, ce load = 0, sr load = 15 PRIMARY : 1 out of 8 (12%) SECONDARY: 5 out of 8 (62%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 7 + 4(JTAG) out of 280 (3.9%) PIO sites used. 7 + 4(JTAG) out of 105 (10.5%) bonded PIO sites used. Number of PIO comps: 7; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+---------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+---------------+------------+-----------+ | 0 | 0 / 26 ( 0%) | - | - | | 1 | 6 / 26 ( 23%) | 3.3V | - | | 2 | 0 / 28 ( 0%) | - | - | | 3 | 0 / 7 ( 0%) | - | - | | 4 | 0 / 8 ( 0%) | - | - | | 5 | 1 / 10 ( 10%) | 3.3V | - | +----------+---------------+------------+-----------+ Total placer CPU time: 6 secs Dumping design to file Picture_display_impl1.dir/5_1.ncd. ----------------------------------------------------------------- INFO - par: ASE feature is off due to non timing-driven settings. ----------------------------------------------------------------- 0 connections routed; 2300 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 9 secs Start NBR router at 17:23:10 11/09/16 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 17:23:10 11/09/16 Start NBR section for initial routing at 17:23:10 11/09/16 Level 4, iteration 1 70(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 10 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 17:23:11 11/09/16 Level 4, iteration 1 30(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 10 secs Level 4, iteration 2 18(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 10 secs Level 4, iteration 3 6(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 10 secs Level 4, iteration 4 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 10 secs Level 4, iteration 5 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 10 secs Start NBR section for re-routing at 17:23:11 11/09/16 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 10 secs Start NBR section for post-routing at 17:23:11 11/09/16 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack<setup> : <n/a> Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 10 secs Total REAL time: 11 secs Completely routed. End of route. 2300 routed (100.00%); 0 unrouted. Checking DRC ... No errors found. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file Picture_display_impl1.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = <n/a> PAR_SUMMARY::Timing score<setup/<ns>> = <n/a> PAR_SUMMARY::Worst slack<hold /<ns>> = <n/a> PAR_SUMMARY::Timing score<hold /<ns>> = <n/a> PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 11 secs Total REAL time to completion: 12 secs par done! Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.