Setting log file to 'F:/Picture_display/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file F:/Picture_display/Picture_display.v
(VERI-1482) Analyzing Verilog file F:/Picture_display/LCD_RGB.v
(VERI-1482) Analyzing Verilog file F:/Picture_display/LCD_RAM.v
INFO - F:/Picture_display/Picture_display.v(18,8-18,23) (VERI-1018) compiling module Picture_display
INFO - F:/Picture_display/Picture_display.v(18,1-60,10) (VERI-9000) elaborating module 'Picture_display'
INFO - F:/Picture_display/LCD_RGB.v(18,1-312,10) (VERI-9000) elaborating module 'LCD_RGB_uniq_1'
INFO - F:/Picture_display/LCD_RAM.v(8,1-572,10) (VERI-9000) elaborating module 'LCD_RAM_uniq_1'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_3'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_4'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_5'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_6'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_7'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_8'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
INFO - C:/lscc/diamond/3.7_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
WARNING - F:/Picture_display/Picture_display.v(56,1-56,17) (VERI-1330) actual bit length 127 differs from formal bit length 132 for port Data
WARNING - F:/Picture_display/Picture_display.v(57,1-57,17) (VERI-1330) actual bit length 128 differs from formal bit length 132 for port Q
Done: design load finished with (0) errors, and (2) warnings